Bit ordering for packetised serial data transmission on an integrated circuit

A method of transmitting data within an integrated circuit, said method comprising the steps of:

• generating a transaction at a master device;
• dividing said transaction into a plurality of transmission packets;
• serially transmitting said plurality of transmission packets;
• serially receiving said plurality of transmission packets;
• combining said plurality of transmission packets to reform said transaction;
• and
• processing said transaction within a slave device;
• wherein
• said step of dividing operates such that one or more bits within said transaction that are not needed by said slave device are not allocated to a transmission packet and are not sent to said slave device.

An integrated circuit comprising:

• a master device operable to generate a transaction;
• a transaction divider operable to divide said transaction into a plurality of transmission packets;
• a serial transmitter operable to serially transmit said plurality of transmission packets;
• a serial receiver operable to serially receive said plurality of transmission packets;
• a transaction combiner operable to combine said plurality of transmission packets to reform said transaction;
• and
• a slave device operable to process said transaction;
• wherein
• said processing within said slave device is dependent upon at least a part of a multi-bit portion of said transaction;
• said transaction divider is operable to allocate bits within said transaction to transmission packets in accordance with a priority ordering with higher priority bits being allocated to transmission packets transmitted before transmission packets containing lower priority bits;
• and
• bits within said multi-bit portion required by said slave device to commence said step of processing have a higher priority and are allocated to one or more transmission packets to be serially transmitted before one or more transmission packets carrying lower priority bits of said multi-bit portion;
• such that
• said slave device can commence processing in response to said transaction after said transmission packets carrying said higher priority bits of said multi-bit portion have been received at said slave device and before said transmission packets carrying said lower priority bits of said multi-bit portion have been received at said slave device.

An interconnect circuit for use within an integrated circuit comprising:

• a transaction divider operable to divide a transaction received from a master device into a plurality of transmission packets;
• a serial transmitter operable to serially transmit said plurality of transmission packets;
• a serial receiver operable to serially receive said plurality of transmission packets;
• and
• a transaction combiner operable to combine said plurality of transmission packets to reform said transaction for processing by a slave device;
• wherein
• said processing within said slave device is dependent upon at least a part of a multi-bit portion of said transaction;
• said transaction divider is operable to allocate bits within said transaction to transmission packets in accordance with a priority ordering with higher priority bits being allocated to transmission packets transmitted before transmission packets containing lower priority bits;
• and
• bits within said multi-bit portion required by said slave device to commence said step of processing have a higher priority and are allocated to one or more transmission packets to be serially transmitted before one or more transmission packets carrying lower priority bits of said multi-bit portion;
• such that
• said slave device can commence processing in response to said transaction after said transmission packets carrying said higher priority bits of said multi-bit portion have been received at said slave device and before said transmission packets carrying said lower priority bits of said multi-bit portion have been received at said slave device.

An interconnect circuit design tool when executed on a controller, said tool comprising:

• bit priority specifying code configured to specify a priority ordering of bits within a transaction to a slave device upon an integrated circuit, one or more bits with a higher priority when received by said slave device permitting said slave device to commence processing of said transaction prior to receiving bits of a lower priority;
• allocating code, responsive to said priority ordering, configured to determine an allocation of bits of said transaction into respective transmission packets to be serially transmitted in a transmission order from a master device to said slave device;
• and
• transaction divider forming code configured to form a design for a transaction divider to divide a transaction into a sequence of serially transmitted transmission packets in accordance with said allocation of bits;
• and
• transaction combiner forming code configured to form a design for a transaction combiner to combine said sequence of serially transmitted transmission packets to reform said transaction.