Credit management when resource granularity is larger than credit granularity
AssigneeApple Inc.
InventorsJames Wang, Zongjian Chen
Life of this patent
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AssigneeApple Inc.
InventorsJames Wang, Zongjian Chen
Estimating the term…
In one embodiment, a receiver on a credit-based flow-controlled interface is configured to free one or more data credits early when a data payload is received that incurs fewer unused data credits within a buffer memory that is allocated at a coarser granularity than the data credits. In another embodiment, header credits and data credits are dynamically adjusted based on actual packet data payload sizes.
An apparatus comprising:
A method comprising:
An apparatus comprising:
An apparatus comprising:
A method, in a receiver configured to manage flow control credits for an interface to which the receiver is coupled during use, wherein each packet received on the interface comprises a header and optionally data, and wherein the header is measured in terms of a header credit for flow control on the interface, and wherein data is measured in terms of one or more data credits for flow control on the interface, each data credit representing a fixed number of data bytes, the method comprising:
Dependencies are inferred from the claim text.
From the US filing history. Foreign family members aren’t listed.
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Using universal interface adapter: for adaptation of a particular data processing system to different peripheral devices
Traffic control in data switching networks: flow control; Congestion control
Flow control; Congestion control: credit based
Packet switching elements: buffering arrangements
About 2 years 7 months of term left · ends 20 May 2029 (estimated)
1. Field of the Invention
This invention is related to digital systems and, more particularly, to credit management for credit-based flow control mechanisms for interfaces in digital systems.
2. Description of the Related Art
The following detailed description makes reference to the accompanying drawings, which are now briefly described.
FIG. 1 is a block diagram of one embodiment of a digital system.
FIG. 2 is a block diagram of one embodiment of memory buffer allocation.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description. As used throughout this application, the word “may” is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words “include”, “including”, and “includes” mean including, but not limited to.
Turning now to FIG. 1, a block diagram of one embodiment of a system 10 is shown. In the illustrated embodiment, the system 10 includes a transmitter 12, a receiver 14, a buffer memory 16, and optionally a packet target 18. The transmitter is coupled to an interface 20 to which the receiver 14 is also coupled. The buffer memory 16 is coupled to the receiver 14 and the target 18.
The transmitter 12 is configured to maintain header credits and data credits, which indicate how much packet header and packet data traffic the receiver 14 is currently able to accept. For example, in FIG. 1, the transmitter 12 may include a header credit register 22 and a data credit register 24. During initialization of the system 10, and possibly at other points during operation at which the interface 20 is reset, the receiver 14 may determine the number of header credits and data credits to advertise to the transmitter 12. The transmitter 12 may initialize the registers 22 and 24 with the advertised credits. As the transmitter 12 transmits packet headers and packet data, the transmitter 12 may deduct the credits consumed by the transmitted headers and data. The receiver 14 may transmit freed credits back to the transmitter 12, which may add the freed credits to the registers 22 and 24. Thus, at any given point in time, the transmitter 12 may control how much information is transmitted over the interface 20 responsive to the credits in the registers 22 and 24. If not enough credits are available for a given transmission, for example, the transmitter 12 may delay transmission until the needed number of credits become available.