Method and memory device providing reduced quantity of interconnections
AssigneeMicron Technology, Inc.
InventorRobert M. Walker
Life of this patent
Estimating the term…
Abstract
Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion of the address of the next row of memory cells to be activated is embedded in a command related to the previously activated row of memory cells. The next row of memory cells is subsequently activated according to a concurrently received second portion of the address of the next row of memory cells also received over the address bus. The portioning of the address signals can reduce the width of the address bus and, therefore, the number of required respective external interconnections.
Claims15
A method for reducing a quantity of interconnections on a synchronous memory comprising:
- inputting on a first command bus cycle a first command and a first portion of an address for a next row of memory cells to be activated;
- and
- inputting on a second command bus cycle after the first command bus cycle a second command and a second portion of the address for the next row of memory cells to be activated, the second command for activating the next row of memory cells according to a row address including a combination of the first portion of the address and the second portion of the address.
A memory device, comprising:
- a memory array including rows of memory cells;
- and
- a controller configured to sample a command bus and an address bus on a same edge of a clock cycle and further configured to:
- concurrently receive a first command over the command bus and, over the address bus, a first portion of an address of a next row of memory cells in the memory array to be activated;
- subsequently receive an activate command over the command bus and, over the address bus, a second portion of the address of the next row of memory cells in the memory array to be activated;
- and
- activate the next row of memory cells in response to the activate command with a row address of the next row including the first portion of the address and the second portion of the address.
Dependencies are inferred from the claim text.