High speed DRAM architecture with uniform access latency
AssigneeMosaid Technologies Incorporated
InventorPaul Demone
Life of this patent
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Abstract
A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.
Claims14
A method of reading data in a random access memory comprising:
- providing a first memory address and a read command on a first edge of a clock signal;
- activating a first word line corresponding to a first segment of the first memory address;
- selecting a bit line corresponding to a second segment of the first memory address;
- sensing data in a memory storage element coupled to the word line and the bit line;
- restoring the data in the memory storage element to a partial charge storage level;
- terminating the restoring of data in the memory storage element responsive to a second edge of the clock signal;
- and
- providing a second memory address on the second edge of the clock signal.
Dependencies are inferred from the claim text.