Multi-stage parallel data transfer
AssigneeSeagate Technology LLC
InventorsYong Lu, Harry Hongyue Liu, Hai Li, Andrew John Carter, Daniel Reed
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Abstract
Apparatus and associated method for transferring data to memory, such as resistive sense memory (RSM). In accordance with some embodiments, input data comprising a sequence of logical states are transferred to a block of memory by concurrently writing a first logical state from the sequence to each of a first plurality of unit cells during a first write step, and concurrently writing a second logical state from the sequence to each of a second non-overlapping plurality of unit cells during a second write step.
Claims20
A method comprising a step of transferring input data comprising a sequence of logical states to a block of memory by concurrently writing a first logical state from the sequence to each of a first plurality of unit cells during a first write step, and concurrently writing a second logical state from the sequence to each of a second non-overlapping plurality of unit cells during a second write step.
An apparatus comprising:
- a memory array comprising a block of unit cells;
- and
- a controller which transfers input data comprising a sequence of logical states to the block of unit cells by concurrently writing a first logical state from the sequence to each of a first plurality of the unit cells during a first write step, and concurrently writing a second logical state from the sequence to each of a second plurality of the unit cells during a second write step, wherein the first plurality and second plurality of unit cells are mutually exclusive.
An apparatus comprising a memory array comprising a block of unit cells and a controller which transfers input data comprising a sequence of logical states into a buffer adjacent the block of unit cells by concurrently writing a first logical state from the sequence to each of a first plurality of the unit cells during a first write step, and concurrently writing a second logical state from the sequence to each of a second plurality of the unit cells during a second write step, wherein the first plurality and second plurality of unit cells are mutually exclusive, and wherein the controller identifies the respective configurations and locations of the respective first and second logical states in the loaded sequence.
Dependencies are inferred from the claim text.