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US 8,045,409 B2Granted
Semiconductor memory device
AssigneeRenesas Electronics Corporation
InventorsTakuya Hirota, Takao Yanagida
Life of this patent
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AssigneeRenesas Electronics Corporation
InventorsTakuya Hirota, Takao Yanagida
Estimating the term…
A semiconductor memory device includes a plurality of memory cells that are arranged at intersections of a word line with bit line pairs, a precharge circuit that is arranged for each of the bit line pairs and is configured to precharge each of the bit line pairs, and a Y-switch circuit that is arranged for each of the bit line pairs and is configured to select each of the bit line pairs. The semiconductor memory device further includes a mode switching unit that switches the normal mode and the test mode in accordance with a mode selection signal that is externally supplied, a plurality of individual control units that control operation of each of the precharge circuits in accordance with operation of each of the Y-switch circuits in the normal mode, and a block control unit that collectively turns off all of the precharge circuits in the test mode.
A semiconductor memory device comprising:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
From the US filing history. Foreign family members aren’t listed.
Arrangements for writing information into, or reading information out from, a digital store: bit line control circuits, e.g. drivers, boosters,…
Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing: built-in arrangements for testing, e.g.…
Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals: marginal testing, e.g. race, voltage…
Using transistors: forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable…
About 3 years 6 months of term left · ends 5 May 2030 (estimated)
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device that is suitable for high-speed operation and capable of analyzing detailed failure.
2. Description of Related Art
The above and other exemplary aspects, advantages and features will be more apparent from the following description of certain exemplary embodiments taken in conjunction with the accompanying drawings, in which:
FIG. 1 shows the whole configuration according to a first exemplary embodiment;
FIG. 2 is a timing chart in a normal mode according to the first exemplary embodiment;
The first and second exemplary embodiments can be combined as desirable by one of ordinary skill in the art.
The exemplary embodiments according to the present invention will be described with reference to the drawings in which the same elements are denoted by the same reference symbols.
Now, the first exemplary embodiment according to a semiconductor memory device of the present invention will be described.