Memory-write timing calibration including generation of multiple delayed timing signals

A method of calibrating timing offsets in a memory controller that controls the operation of a memory device, wherein the memory controller is coupled to the memory device via a control signal path and a data signal path, the method comprising:

• generating a plurality of delayed versions of a timing signal that is used to indicate valid write data on the data signal path, wherein a rising edge transition of the timing signal indicates a valid first symbol of the write data, and a falling edge transition of the timing signal indicates a valid second symbol of the write data;
• and
• generating a selected timing signal of the plurality of delayed versions of the timing signal, such that the write data, the selected timing signal and the write command corresponding to the write data arrive at the memory device within a predetermined time period.

A memory control apparatus for controlling the operation of a memory device, wherein the memory control apparatus is to be coupled to the memory device via a control signal path and a data signal path, the memory control apparatus comprising:

• means for generating a plurality of delayed versions of a timing signal that is used to indicate valid write data on the data signal path, wherein a rising edge transition of the timing signal indicates a valid first symbol of the write data, and a falling edge transition of the timing signal indicates a valid second symbol of the write data;
• and
• means for generating a selected timing signal of the plurality of delayed versions of the timing signal, such that the write data, the selected timing signal and the write command corresponding to the write data arrive at the memory device within a predetermined time period.