Latency circuit using division method related to CAS latency and semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsSang-hyuk Kwon, Byung-hoon Jeong
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Abstract
A latency circuit for use in a semiconductor memory device includes a latency control clock generator generating an m-divided division signal from an external clock and at least one latency control clock from the m-divided division signal, wherein m is a natural number greater than or equal to 2. The latency circuit also includes a latency signal generator generating a latency signal in response to the at least one latency control clock, a latency control signal and an internal read command signal, wherein the latency control signal is generated from a column address strobe (CAS) latency and the internal read command signal is generated in response to a received read command.
Claims20
A latency circuit adapted for use in a semiconductor memory device, the latency circuit comprising:
- a latency control clock generator configured to generate an m-divided division signal from an external clock, and generate at least one latency control clock from the m-divided division signal, wherein m is a natural number greater than or equal to 2;
- and
- a latency signal generator configured to generate a latency signal in response to the at least one latency control clock, a latency control signal and an internal read command signal, wherein the latency control signal is generated from a column address strobe (CAS) latency and the internal read command signal is generated in response to a received read command.
A semiconductor memory device comprising:
- an internal read command signal generator configured to generate an internal read command signal in response to a read command synchronously received in relation to an external clock;
- a latency control clock generator configured to generate a phase synchronization signal from the external clock and generate at least one latency control clock signal by m-dividing the phase synchronization signal, wherein m is a natural number greater than or equal to 2;
- and
- a latency signal generator configured to generate a latency signal in response to the at least one latency control clock, a latency control signal and an internal read command signal, wherein the latency control signal is generated from a column address strobe (CAS) latency and the internal read command signal is generated in response to a received read command;
- and
- an output unit configured to output read data in response to the internal read command signal and the latency signal.
Dependencies are inferred from the claim text.