Supporting scan functions within memories
AssigneeArm Limited
InventorsYew Keong Chong, Gus Yeung, Paul Darren Hoxey, Paul Stanley Hughes, Gary Robert Waggoner
Life of this patent
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AssigneeArm Limited
InventorsYew Keong Chong, Gus Yeung, Paul Darren Hoxey, Paul Stanley Hughes, Gary Robert Waggoner
Estimating the term…
A memory is disclosed comprising: a storage array for storing data; and access circuitry for transmitting data to and from the storage array. The access circuitry forms a data path for inputting and outputting data to the storage array. The access circuitry comprises a latch configured to latch in response to a first phase of a first clock signal and a further latch configured to latch in response to a second phase of a second clock signal, the further latch comprises an output latch for outputting the data from the storage array, and the first and second clock signals are synchronized with each other. The memory further comprises: a multiplexer, a scan input and a scan enable input, the multiplexer being responsive to an asserted scan enable signal at the scan enable input to form a scan path comprising the latch and the further latch connected together to form a master slave flip flop, such that scan data input at the scan input passes through the master slave flip flop and not through the storage array while the scan enable signal is asserted and is output by the output latch.
A memory comprising:
A method of providing a scan function to a memory, said memory comprising:
A data storage means comprising:
Dependencies are inferred from the claim text.