Memory and reading method thereof
AssigneeMacronix International Co., Ltd.
InventorYung-Feng Lin
Life of this patent
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Abstract
A reading method applied for a memory, which includes a cell row including a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line is provided. The reading method comprises the following steps. Firstly, the first bit line coupled to a first terminal of the first memory cell is selected for reading the first memory cell in a time period. Next, the second terminal of the first memory cell is discharged via the second bit line coupled to the second memory cell in the time period.
Claims10
A memory, comprising:
- a memory array, comprising a first memory cell and a second memory cell situated on a selected cell row of the memory array;
- and
- a first bit line and a second bit line respectively coupled to the first and the second memory cells;
- a discharge circuit comprising at least two discharge paths, corresponding to a sense amplifier, for discharging the second bit line when the first memory cell is read;
- an address decoder, enabling the selected cell row in response to a row address, and providing a selection signal and a discharge signal in a time period;
- and
- a Y-multiplexer, connecting the second bit line to the discharge circuit in response to the selection signal, so that the discharge circuit discharges the second bit line in response to the discharge signal.
A reading method for a memory, the memory comprising a cell row, the cell row comprising a first memory cell coupled to a first bit line, and a second memory cell coupled to a second bit line, the reading method comprising:
- selecting the first bit line coupled to a first terminal of the first memory cell for reading the first memory cell in a time period;
- and
- providing a discharge unit coupled to the second bit line, for discharging a second terminal of the first memory via the discharge unit when the first memory cell is read, wherein the step of providing the discharging unit further comprising:
- enabling the second memory cell, which short-connects the second bit line to the second terminal of the first cell in response to a row address;
- connecting the second bit line to the discharge circuit in response to a selection signal;
- and
- enabling the discharge circuit to discharge the voltage on the second terminal of the first memory cell to a ground voltage in response to a discharge signal.
Dependencies are inferred from the claim text.