US 8,045,395 B2 · Circuits, systems and methods for driving high and low voltages on bit lines in non-volatile memory

Abstract

An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias transistor through which an input signal is coupled to the respective bit line. The bit line driver system includes a bias voltage circuit that generates a bias voltage that is coupled to the respective gates of the bias transistors. The bias voltage circuit initially accelerates the charging of the transistor gates, and subsequently completes charging the gates at a slower rate. The bias voltage is generated using a diode-coupled transistor having electrical characteristics the match those of the bias transistors so that the bias voltage varies with process or temperature variations of the integrated circuit in the same manner as the threshold voltage of the bias transistors vary with process or temperature variations.

Claims23

Dependent claims

A bit line driver system coupled to a plurality of bit lines, the bit lines being coupled to respective columns of non-volatile memory cells, the bit line driver system comprising:

a plurality of bit line drivers, each bit line driver being coupled to a respective one of the bit lines, each of the bit line drivers including a bias transistor through which an input data signal is coupled to the respective bit line, each of the bias transistors having a respective gate;
a current generator generating a reference current;
a current mirror circuit coupled to receive the reference current from the current generator, the current mirror including a diode-coupled reference transistor through which a mirrored current is conducted so that the reference transistor generates a reference voltage between a source and a drain of the reference transistor;
and
a bias voltage generator coupled to receive the reference voltage from the current mirror circuit, the bias voltage generator being operable to generate a bias voltage corresponding to the reference voltage, the bias voltage generator being coupled to supply the bias voltage to the respective gates of the bias transistors.

2 more elements

A non-volatile memory device comprising:

an array of non-volatile memory cells arranged in columns, each column of memory cells coupled by a respective bit line;
a plurality of bit line drivers, each bit line driver being coupled to a respective one of the bit lines, each of the bit line drivers including a bias transistor through which an input data signal is coupled to the respective bit line, each of the bias transistors having a respective gate;
a current generator generating a reference current;
a current mirror circuit coupled to receive the reference current from the current generator, the current mirror including a diode-coupled reference transistor through which a mirrored current is conducted so that the reference transistor generates a reference voltage between the source and drain of the reference transistor;
and
a bias voltage generator coupled to receive the reference voltage from the current mirror circuit, the bias voltage generator being operable to generate a bias voltage corresponding to the reference voltage, the bias voltage generator being coupled to supply the bias voltage to the respective gates of the bias transistors.

3 more elements

A processor-based system comprising:

a processor operable to process data and to provide memory commands and addresses;
an input device coupled to the processor;
an output device coupled to the processor;
and
a non-volatile memory device, comprising:
an array of non-volatile memory cells arranged in columns, each column of memory cells coupled by a respective bit line, the memory cells in the array being programmable to multiple charge levels corresponding to different respective bit states;
a plurality of bit line drivers, each bit line driver being coupled to a respective one of the bit lines, each of the bit line drivers including a bias transistor through which an input data signal is coupled to the respective bit line, each of the bias transistors having a respective gate;
a current generator generating a reference current;
a current mirror circuit coupled to receive the reference current from the current generator, the current mirror including a diode-coupled reference transistor through which a mirrored current is conducted so that the reference transistor generates a reference voltage between the source and drain of the reference transistor;
and
a bias voltage generator coupled to receive the reference voltage from the current mirror circuit, the bias voltage generator being operable to generate a bias voltage corresponding to the reference voltage, the bias voltage generator being coupled to supply the bias voltage to the respective gates of the bias transistors.

8 more elements

Dependencies are inferred from the claim text.

Circuits, systems and methods for driving high and low voltages on bit lines in non-volatile memory

Life of this patent

Circuits, systems and methods for driving high and low voltages on bit lines in non-volatile memory

Life of this patent

Abstract

Claims23