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US 8,045,392 B2Granted
Multiple level programming in a non-volatile memory device
AssigneeRound Rock Research, LLC
InventorHagop A. Nazarian
Life of this patent
Estimating the term…
Abstract
The programming method of the present invention minimizes program disturb by initially programming cells on the same word line with the logical state having the highest threshold voltage. The remaining cells on the word line are programmed to their respective logical states in order of decreasing threshold voltage levels.
Claims18
A method for programming a flash memory device, the method comprising:
- programming a first page, of a plurality of pages, with a series of incrementing first programming voltage pulses that increment to a first maximum voltage and a series of incrementing second programming voltage pulses that increment to a second maximum voltage, the first maximum voltage being greater than the second maximum voltage;
- performing two first verification pulses after each first programming voltage pulse;
- performing two second verification pulses after each second programming voltage pulse, wherein each first verification pulse is a higher voltage than each second verification pulse;
- and
- programming a second page of the plurality of pages with a series of third incrementing programming voltage pulses that increment to a third maximum voltage that is less than both the first and the second maximum voltages.
2 more elements
A method for programming a flash memory device having a plurality of word lines, the method comprising:
- applying, to a wordline of the plurality of word lines, a series of incrementing first programming voltage pulses that increment to a first threshold voltage;
- applying two first verification pulses to the wordline between each first programming voltage pulse;
- applying, to the wordline, a series of incrementing second programming voltage pulses that increment to a second threshold voltage, the second threshold voltage being less than the first threshold voltage;
- applying two second verification pulses to the wordline between each second programming voltage pulse, wherein each first verification pulse is a higher voltage than each second verification pulse;
- and
- applying, to the wordline, a series of third incrementing programming voltage pulses that increment to a third threshold voltage, the third threshold voltage being less than both the first and second threshold voltages.
3 more elements
A flash memory device comprising:
- a memory array comprising a plurality of word lines that are each coupled to a plurality of multiple level memory cells, the memory array organized into a plurality of pages;
- and
- a control circuit that is coupled to control programming of the memory array, the control circuit configured to initially program a first page, with two highest distributions using first programming pulses, and subsequently program a second page with lower distributions using second programming pulses, wherein the control circuit is further configured to control generation of two first verification pulses to be applied between each first programming pulse while programming the first page and two second verification pulses applied to be applied between each second programming pulse while programming the second page, the two first verification pulses being applied before the two second verification pulses, wherein each first verification pulse is a higher voltage than each second verification pulse.
An electronic system comprising:
- a processor for generating memory signals;
- and
- a memory device, coupled to the processor, for operating in response to the memory signals, the memory device comprising:
- a memory array comprising a plurality of word lines that are each coupled to a plurality of multiple level memory cells;
- and
- a control circuit that is coupled to program the memory array, the control circuit configured to initially program a first page, with two highest distributions using first program pulses, and subsequently program a second page with lower distributions using second program pulses, wherein the control circuit is further configured to control generation of two first verification pulses to be applied between each first program pulse while programming the first page and two second verification pulses to be applied between each second program pulse while programming the second page, wherein each first verification pulse is applied before each second verification pulse, each first verification pulse having a higher voltage level than each second verification pulse.
3 more elements
Dependencies are inferred from the claim text.