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US 8,045,389 B2Granted
Semiconductor memory device
AssigneePanasonic Corporation
InventorsHidenari Kanehara, Yasuhiro Agata, Norihiko Sumitani, Akira Masuo
Life of this patent
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Abstract
A dummy cell array is provided in a memory cell array, and an intermediate buffer is provided between input/output circuits, whereby control signals to the input/output circuits can be operated at high speed and with a high frequency while the area increasing effect is reduced even in a memory with a large bit width.
Claims11
A semiconductor memory device including:
- a memory cell array including memory cells configured to store data and arranged in an array;
- a first circuit configured to have at least one of a function of outputting data from the memory cells and a function of inputting data to the memory cells;
- and
- a second circuit configured to have at least one of a function of outputting data from the memory cells and a function of inputting data to the memory cells,
- wherein
- at least one line of dummy cells other than the memory cells configured to store the data is provided in the memory cell array and arranged in parallel with a bit line direction of the memory cells, and
- a buffer circuit configured to buffer a control signal to the first or second circuit is provided between the first and second circuits in a region extending in the bit line direction from the dummy cell line.
4 more elements
Dependencies are inferred from the claim text.