Flash memory devices and erasing methods thereof

An erasing method for a flash memory device, comprising:

• erasing a plurality of memory cells of a selected memory block;
• and
• post-programming the erased plurality of memory cells to have a threshold voltage distribution with a lowest level that is in a voltage range that is near 0V,
• wherein post-programming the plurality of erased memory cells comprises:
• first post-programming the plurality of memory cells in the memory block in one operation wherein the memory block is first programmed as a unit;
• and
• second post-programming the plurality of memory cells in the memory block in groups according to word lines, wherein the memory block is second programmed in the unit of word line,
• wherein first post-programming the plurality of memory cells comprises verify reading a result of the first post-programming with a predetermined verifying voltage,
• wherein second post-programming the plurality of memory cells comprises verify reading a result of the second post-programming with a predetermined verifying voltage,
• wherein if there is an increase of voltage gap between a level of a control signal for controlling a precharging level of a selected bit line during a precharging period of the verify reading and a level of the control signal applied during a sensing period of the verify reading, recognizing the verifying voltage as a negative voltage, and
• wherein, during the precharging period, the verifying voltage is decreased and the level of the control signal applied is increased.

A flash memory device comprising:

• a memory cell array including a plurality of memory blocks, wherein each of the plurality of memory blocks includes a plurality of memory cells;
• a control circuit that is operable to control a post-programming operation of erased memory cells to have a threshold voltage distribution with a lowest level that is in a voltage range that is near 0V;
• a voltage generator that is operable to generate a plurality of voltages that are used for the post-programming operation and a verify reading to the post-programming operation in response to control by the control circuit;
• and
• a read/write circuit that is operable to conduct the post-programming operation and verify reading in response to control by the control circuit,
• wherein if there is an increase of voltage gap between a level of a control signal for controlling a precharging level of a selected bit line during a precharging period of the verify reading and a level of the control signal applied during a sensing period of the verify reading, a verifying voltage for the verify reading includes a negative voltage, and
• wherein, during the precharging period, the level of the verifying voltage decreases and the level of the control signal applied increases.