Flash memory device with multi level cell and burst access method therein
AssigneeSamsung Electronics Co., Ltd.
InventorsJung-Woo Lee, Jae-Yong Jeong
Life of this patent
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Abstract
A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words to be stored in the memory cells, and an output circuit configured to output a group of the words using the sets of bits from one sensing, at least as early as during a subsequent sensing of sets of bits.
Claims14
A method of reading a semiconductor memory device including a plurality of multi-level memory cells (MLC) having most significant bits and at least one additional set of bits, the method comprising:
- sensing the most significant bits of the plurality of MLCs;
- and
- simultaneously outputting the most significant bits of the plurality of MLCs while sensing second sets of bits of the at least one additional set of bits of the plurality of MLCs,
- wherein outputting the most significant bits includes combining most significant bits of the plurality of MLCs to form words.
A method of reading a semiconductor memory device comprising:
- reconfiguring a designated burst length of input word data into a first part including at least one first word and a second part including at least one second word;
- dividing the first word into a plurality of segments and storing the first part of the designated burst length into a most significant bit portion of a plurality of multi-level memory cells, such that each segment of the first word is stored in a most significant bit portion of different multi-level memory cells;
- dividing the second word into a plurality of segments and storing the second part of the designated burst length into a least significant bit portion of the plurality of multi-level memory cells, such that each segment of the second word is stored in a least significant bit portion of the different multi-level memory cells;
- sensing the first part stored in the most significant bit portion of the plurality of multi-level memory cells at a first time;
- and
- simultaneously outputting the sensed first part of the plurality of multi-level memory cells including the first word while sensing the second part stored in the least significant bit portion of the plurality of multi-level memory cells at a second time.
A method of reading a semiconductor memory device having a plurality of multi-level cells, each multi-level cell having a plurality of sets of bits, the method comprising:
- sensing the most significant bits from among the plurality of sets of bits of each of the multi-level cells;
- and
- outputting the sensed most significant bits to form at least one word while simultaneously sensing next-significant bits from among the plurality of sets of bits of each of the multi-level cells.
Dependencies are inferred from the claim text.