Method and apparatus for programming memory cell array

A method for reducing disturbs in an array of memory cells, comprising:

• selecting a first row of the array of memory cells for a write operation, the first row comprising a first memory cell in a first column of the array of memory cells and a second memory cell in a second column of the array of memory cells, wherein the first memory cell connected between a first bit line and a first source line and the second memory cell connected between a second bit line and a second source line;
• connecting the first bit line to the first source line and the second bit line to the second source line, wherein the first source line is equipotential with the first bit line and the second source line is equipotential with the second bit line;
• erasing the first row of the array of memory cells;
• programming the first memory cell and inhibiting the second memory cell, wherein the second column includes a third memory cell in a second row of the array and the first column includes a fourth memory cell in the second row of the array of memory cells, wherein the third memory cell is connected between the second bit line and the second source line and the fourth memory cell is connected between the first bit line and the first source line;
• and
• applying a first reference voltage on a first write line shared by the first memory cell and the second memory cell, wherein programming the first memory cell comprises applying a programming voltage on the first bit line, and inhibiting the second memory cell comprises applying an inhibit voltage on the second bit line.

An apparatus, comprising:

• a memory array comprising memory cells arranged in rows and columns;
• and
• a memory controller coupled to the memory array, comprising:
• a row controller configured to select a first row of the memory array for a write operation and to deselect a second row of the memory array, wherein the first row comprises a first memory cell coupled between a first bit line and a first source line in a first column of the memory array and a second memory cell coupled between a second bit line and a second source line in a second column of the memory array, wherein each of the memory cells includes a memory transistor and a pass transistor;
• and
• a column controller configured to connect the first bit line to the first source line and to connect the second bit line to the second source line, the column controller further configured to erase the first row of the memory array.

An apparatus, comprising:

• a memory array comprising memory cells arranged in rows and columns;
• and
• a memory controller coupled to the memory array, comprising:
• a row controller configured to select a first row of the memory array for a write operation and to deselect a second row of the memory array, wherein the first row comprises a first memory cell coupled between a first bit line and a first source line in a first column of the memory array and a second memory cell coupled between a second bit line and a second source line in a second column of the memory array;
• and
• a column controller configured to connect the first bit line to the first source line and to connect the second bit line to the second source line, the column controller further configured to erase the first row of the memory array, wherein the memory controller is further configured to program the first memory cell and to inhibit the second memory cell from programming, wherein the second row comprises a third memory cell coupled between the second bit line and the second source line and a fourth memory cell coupled between the first bit line and the first source line, wherein the row controller is configured to apply a first reference voltage on a first write line shared by the first memory cell and the second memory cell, wherein to program the first memory cell the column controller is configured to apply a programming voltage on the first bit line, and wherein to inhibit the second memory cell the column controller is configured to apply an inhibit voltage on the second bit line.

An apparatus, comprising:

• means for selecting a row of memory cells in a memory array for a write operation, wherein each of the memory cells includes a memory transistor and a pass transistor;
• means for selectively connecting source lines of the memory cells to bit lines of the memory cells to conform the voltages on the source lines to voltages on the bit lines;
• and
• means for selectively programming and erasing memory cells in the row of memory cells.