Phase change memory

#1. Field of the Invention

#The invention relates to the phase change memory, and more particularly to the reference memory unit of the phase change memory.

#2. Description of the Related Art

#The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

#FIG. 1 is a schematic diagram of a conventional memory array with a parallel-connected reference memory array announced by Ovonyx Inc. in 2001;

#FIG. 2 is a block diagram of an embodiment of the phase change memory 200 of the invention;

#The following description is of the contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

#FIG. 2 is a block diagram of an embodiment of the phase change memory 200 of the invention. The phase change memory 200 comprises a primary memory block 220, a reference memory block 230 and a comparison circuit 240.

#The primary memory block 220 comprises a plurality of primary memory units 221 arranged in at least one column and at least one row to form a memory array, such as the columns C1 to C4 and rows R1 to R4. The primary memory block 220 further comprises at least one column line and at least one row line, such as the column limes CL1 to CL 4 and row lines RL1 to RL4, respectively coupled to the corresponding primary memory units 221. Each of the primary memory units 221 comprises a transistor QM and a recording layer RML coupled to the transistor QM and a reference voltage VA. It is noted that the locations of the transistor QM and the recording layer RML can be interchangeable.