Variable resistance memory devices including arrays of different sizes

A variable resistance memory device comprising:

• a high-density array of first variable resistance memory cells on an integrated circuit chip, wherein each of the first variable resistance memory cells has a first cell size;
• a high-speed array of second variable resistance memory cells on the integrated circuit chip, wherein each of the second variable resistance memory cells has a second cell size different than the first cell size;
• and
• a memory interface including a first interface configured to access the high-density array and a second interface configured to access the high-speed array, and wherein the first and second interfaces are physically integrated in the memory interface.

A variable resistance memory device comprising:

• a first resistive memory array on an integrated circuit chip, wherein the first resistive memory array includes a first plurality of bitlines, a first plurality of wordlines, and a first plurality of variable resistance memory cells, wherein each of the variable resistance memory cells of the first plurality is electrically coupled between one of the first plurality of bitlines and one of the first plurality of wordlines;
• a second resistive memory array on the integrated circuit chip, wherein the second resistive memory array includes a second plurality of bitlines, a second plurality of wordlines, and a second plurality of variable resistance memory cells, wherein each of the variable resistance memory cells of the second plurality is electrically coupled between one of the second plurality of bitlines and one of the second plurality of wordlines, wherein the first and second resistive memory arrays have different sizes;
• and
• a sense amplifier configured to read data from the first resistive memory array using voltage sensing and to read data from the second resistive memory array using current sensing.

A variable resistance memory device comprising:

• a first array of first variable resistance memory cells on an integrated circuit chip, wherein each of the first variable resistance memory cells has a first size;
• a second array of second variable resistance memory cells on the integrated circuit chip, wherein each of the second variable resistance memory cells has a second size different than the first size;
• a memory interface on the integrated circuit chip, wherein the memory interface includes a first interface configured to access the first array of the first variable resistance memory cells and a second interface configured to access the second array of the second variable resistance memory cells;
• and
• a mode controller configured to control a data latency and/or a data access speed in response to a mode selection signal.