Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorHiroshi Maejima
Life of this patent
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Abstract
A semiconductor memory device comprising: a memory cell array in which memory cells each containing a variable resistive element and a rectifier element connected in series are arranged at intersections of a plurality of first wirings and a plurality of second wirings; and a control circuit for selectively driving said first wirings and said second wirings; wherein said control circuit applies a first voltage to said selected first wiring, and changes said first voltage based on the position of said selected memory cell within said memory cell array to apply a second voltage to said selected second wiring, so that a predetermined potential difference is applied to a selected memory cell arranged at the intersection between said selected first wiring and said selected second wiring.
Claims11
A semiconductor memory device comprising:
- a memory cell array in which memory cells each containing a variable resistive element and a rectifier element connected in series are arranged at intersections of a plurality of first wirings and a plurality of second wirings;
- and
- a control circuit for selectively driving said first wirings and said second wirings;
- wherein said control circuit applies a first voltage to a selected first wiring, and changes said first voltage based on the position of a selected memory cell within said memory cell array to apply a second voltage to a selected second wiring, so that a predetermined potential difference is applied to the selected memory cell arranged at the intersection between said selected first wiring and said selected second wiring.
Dependencies are inferred from the claim text.