Non-volatile memory cell with complementary resistive memory elements
AssigneeSeagate Technology LLC
InventorsHyung-Kyu Lee, YoungPil Kim, Chulmin Jung
Life of this patent
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Abstract
A non-volatile memory cell and method of writing data thereto. In accordance with some embodiments, the memory cell includes first and second resistive memory elements (RMEs) configured to concurrently store complementary programmed resistive states. The first RME is programmed to a first resistive state and the second RME is concurrently programmed to a second resistive state by application of a common write current in a selected direction through the memory cell.
Claims20
A non-volatile memory array comprising a first non-volatile memory cell connected between first and second bit lines that define a first column and a second non-volatile memory cell connected between third and fourth bit lines that define a second column, each non-volatile memory cell comprising first and second resistive memory elements (RMEs) configured to concurrently store different programmed resistive states in response to application of a common write current in a selected direction through the first and second RMEs of the first non-volatile memory cell, wherein the first and second columns each have a write circuit capable of generating the common write current in opposite directions through the respective first and second columns.
A method comprising:
- providing a non-volatile memory array with a first non-volatile memory cell connected in a first column and a second non-volatile memory cell connected in a second column, each memory cell comprising multiple resistive memory elements (RMEs) configured to concurrently store complementary programmed resistive states;
- applying a first common bidirectional write current through the first non-volatile memory cell with a first write circuit connected within the first column to concurrently program a first RME to a first resistive state and a second RME to a complementary second resistive state;
- and
- applying a second common bidirectional write current through the second non-volatile memory cell with a second write circuit connected within the second column to concurrently program a third RME to the first resistive state and a fourth RME to the complementary second resistive state.
A non-volatile memory cell array comprising first and second columns each having a common column width between respective bit lines, each of the first and second columns further having a memory cell, read circuit, write circuit, and equalization circuit connected between the associated bit lines, each memory cell comprising multiple resistive memory elements (RMEs) configured to concurrently store complementary programmed resistive states responsive to bidirectional currents generated, applied to the associated bit lines, and passed through the RMEs by the write circuit.
Dependencies are inferred from the claim text.