Thin film transistor array panel and a method for manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsYoung-Wook Lee, Jang-Soo Kim
Life of this patent
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Abstract
A thin film transistor array panel includes a substrate; a plurality of gate lines that are formed on the substrate; a plurality of data lines that intersect the gate lines; a plurality of thin film transistors that are connected to the gate lines and the data lines; a plurality of color filters that are formed on upper parts of the gate lines, the data lines, and the thin film transistors; a common electrode that is formed on the color filters and that includes a transparent conductor; a passivation layer that is formed on an upper part of the common electrode; and a plurality of pixel electrodes that are formed on an upper part of the passivation layer and that are connected to a drain electrode of each of the thin film transistors.
Claims57
A thin film transistor array panel comprising:
- a substrate;
- a gate line disposed on the substrate;
- a data line intersecting the gate line;
- a thin film transistor connected to the gate line and the data line;
- a color filter disposed on upper parts of the gate line, the data line, and the thin film transistor;
- a first electrode disposed on the color filter and comprising a transparent conductor;
- a passivation layer disposed on an upper part of the first electrode;
- and
- a second electrode disposed on an upper part of the passivation layer and connected to a drain electrode of the thin film transistor,
- wherein the second electrode comprises a plurality of branch electrodes inclined at an angle to the gate line or the data line, and a connection part connecting the plurality of branch electrodes,
- wherein the color filter comprises an opening and the passivation layer comprises a first contact hole to contact the drain electrode with the second electrode.
A thin film transistor array panel comprising:
- a substrate;
- a gate line disposed on the substrate;
- a data line intersecting the gate line;
- a thin film transistor connected to the gate line and the data line;
- a color filter disposed on the gate line, the data line, and the thin film transistor;
- a first electrode disposed on the color filter;
- a passivation layer disposed on the first electrode;
- a second electrode disposed on the passivation layer and connected to a drain electrode of the thin film transistor;
- and
- a common signal line that is disposed in a same layer as the gate line and that is electrically connected to the first electrode,
- wherein the second electrode comprises a plurality of branch electrodes inclined at an angle to the gate line or the data line, and a connection part for connecting the plurality of branch electrodes.
A thin film transistor array panel comprising:
- a substrate;
- a gate line disposed on the substrate;
- a data line intersecting the gate line;
- a thin film transistor connected to the gate line and the data line;
- a color filter disposed on the gate line, the data line, and the thin film transistor;
- a first electrode disposed on the color filter;
- a passivation layer disposed on the first electrode;
- a second electrode disposed on an upper part of the passivation layer and connected to a drain electrode of the thin film transistor;
- and
- a common signal line that is disposed in a same layer as the gate line and that is electrically connected to the first electrode,
- wherein the color filter comprises an opening and the passivation layer comprises a first contact hole to contact the drain electrode with the second electrode.
A thin film transistor array panel comprising:
- a substrate;
- a gate line disposed on the substrate;
- a data line intersecting the gate line;
- a thin film transistor connected to the gate line and the data line;
- a color filter disposed on the gate line, the data line, and the thin film transistor;
- a first electrode disposed on the color filter;
- a passivation layer disposed on the first electrode;
- a second electrode disposed on an upper part of the passivation layer and connected to a drain electrode of the thin film transistor;
- and
- a common signal line that is disposed in a same layer as the gate line and that is electrically connected to the first electrode,
- wherein the second electrode comprises a plurality of branch electrodes inclined at an angle to the gate line or the data line, and a connection part connecting the plurality of branch electrodes,
- wherein the color filter comprises an opening and the passivation layer comprises a first contact hole to contact the drain electrode with the second electrode.
A thin film transistor array panel comprising:
- a substrate;
- a gate line disposed on the substrate;
- a data line intersecting the gate line;
- a thin film transistor connected to the gate line and the data line;
- a color filter disposed on the gate line, the data line, and the thin film transistor;
- a first electrode disposed on the color filter;
- a passivation layer disposed on the first electrode;
- a second electrode disposed on the passivation layer and connected to a drain electrode of the thin film transistor;
- and
- a common signal line that is disposed in a same layer as the data line and that is electrically connected to the first electrode,
- wherein the second electrode comprises a plurality of branch electrodes inclined at an angle to the gate line or the data line, and a connection part for connecting the plurality of branch electrodes.
A thin film transistor array panel comprising:
- a substrate;
- a gate line disposed on the substrate;
- a data line intersecting the gate line;
- a thin film transistor connected to the gate line and the data line;
- a color filter disposed on the gate line, the data line, and the thin film transistor;
- a first electrode disposed on the color filter;
- a passivation layer disposed on the first electrode;
- a second electrode disposed on an upper part of the passivation layer and connected to a drain electrode of the thin film transistor;
- and
- a common signal line that is disposed in a same layer as the data line and that is electrically connected to the first electrode,
- wherein the color filter comprises an opening and the passivation layer comprises a first contact hole to contact the drain electrode with the second electrode.
A thin film transistor array panel comprising:
- a substrate;
- a gate line disposed on the substrate;
- a data line intersecting the gate line;
- a thin film transistor connected to the gate line and the data line;
- a color filter disposed on the gate line, the data line, and the thin film transistor;
- a first electrode disposed on the color filter;
- a passivation layer disposed on the first electrode;
- a second electrode disposed on an upper part of the passivation layer and connected to a drain electrode of the thin film transistor;
- and
- a common signal line that is disposed in a same layer as the data line and that is electrically connected to the first electrode,
- wherein the second electrode comprises a plurality of branch electrodes inclined at an angle to the gate line or the data line, and a connection part connecting the plurality of branch electrodes,
- wherein the color filter comprises an opening and the passivation layer comprises a first contact hole to contact the drain electrode with the second electrode.
A thin film transistor array panel comprising:
- a substrate;
- a gate line that is formed on the substrate;
- a data line that intersects the gate line;
- a thin film transistor that is connected to the gate line and the data line;
- a plurality of color filters that are disposed on the gate line, the data line, and the thin film transistor;
- a common electrode that is disposed on the color filter and that includes a transparent conductor;
- a passivation layer that is disposed on the common electrode;
- and
- a pixel electrode that is disposed on the passivation layer and that is connected to a drain electrode of each of the thin film transistors,
- wherein a side wall of the color filters is disposed on an upper part of the date line.
Dependencies are inferred from the claim text.