Image display system

An image display system, comprising:

• a first pixel, comprising a first transistor and a first storage capacitor, wherein the first storage capacitor is coupled to the source of the first transistor via a first pixel electrode;
• a second pixel, comprising a second transistor and a second storage capacitor, wherein the second storage capacitor is coupled to the source of the second transistor via a second pixel electrode;
• a third pixel, comprising a third transistor and a third storage capacitor, wherein the third storage capacitor is coupled to the source of the third transistor via a third pixel electrode;
• a scan line, coupling the gates of the first, the second and the third transistors to transport a scan signal to control the conductance of the first, the second, and the third transistors;
• a first data line, coupling the drain of the first transistor, and receiving a voltage data during a first time interval;
• a second data line, coupling the drain of the second transistor, and receiving the voltage data during a second time interval later than the first time interval;
• and
• a third data line, coupling the drain of the third transistor, and receiving the voltage data during a third time interval later than the second time interval;
• wherein the first and second storage capacitors are designed according to the following formulas:
• C
• st
• ⁢
• ⁢
• 1
• =
• Δ
• ⁢
• ⁢
• V
• gate
• ×
• C
• gd
• ⁢
• ⁢
• 1
• Δ
• ⁢
• ⁢
• V
• 1
• +
• V
• f
• ⁢
• ⁢
• 3
• -
• C
• lc
• ⁢
• ⁢
• 1
• -
• C
• gd
• ⁢
• ⁢
• 1
• ,
• and
• C
• st
• ⁢
• ⁢
• 2
• =
• Δ
• ⁢
• ⁢
• V
• gate
• ×
• C
• gd
• ⁢
• ⁢
• 2
• Δ
• ⁢
• ⁢
• V
• 2
• +
• V
• f
• ⁢
• ⁢
• 3
• -
• C
• lc
• ⁢
• ⁢
• 2
• -
• C
• gd
• ⁢
• ⁢
• 2
• ,
• where
• Cst1 and Cst2 represent the capacitance of the first and second storage capacitors, respectively,
• Cgd1 represents the capacitance of the parasitical capacitor coupled between the gate and drain of the first transistor,
• Cgd2 represents the capacitance of the parasitical capacitor coupled between the gate and drain of the second transistor,
• Clc1 and Clc2 represent the capacitance of the liquid crystal capacitors of the first and second pixels, respectively,
• ΔVgate represents the voltage variation at the scan line,
• ΔV1 and ΔV2 represent voltage coupling shifts at the first and second pixel electrodes, respectively, and
• Vf3 represents a third feedthrough voltage which is the voltage variation at the third pixel electrode that varies with the scan signal.