Driver circuit usable for display panel

#The present invention relates to a driver circuit usable for a display panel.

#A conventional driver circuit usable for a display panel such as a liquid crystal display (LCD) panel or an organic electroluminescence (EL) display panel is disclosed by, for example, Japanese Patent Kokai No. 2005-192260 (D1).

#A LCD panel disclosed by the document D1 is provided with an active matrix liquid crystal panel and a drive unit for driving the active matrix liquid crystal panel. The liquid crystal panel is formed from a matrix of liquid crystal display elements placed where plural scanning lines and plural data lines are intersected with each other. The drive unit has plural source drivers connected to the data lines and plural gate drivers connected to the scanning lines, both of which are controlled by a controller. Each of the source drivers includes plural driver circuits capable of providing output signals to the liquid crystal elements, whereby light transmittance of the liquid crystal elements is controlled.

#FIG. 1 is a circuit diagram showing a driver circuit usable for a display panel, which circuit relates to the present invention;

#FIG. 2 is a circuit diagram showing a driver circuit usable for a display panel, which circuit is a first embodiment of the present invention;

#FIG. 3 is a wave form chart showing simulation output voltages generated from driver circuits according to the present invention;

#Embodiments of the present invention will be described below with reference to FIGS. 2 to 5. Components in FIGS. 2, 4, and 5 which operate in the same manner are denoted by the same reference numerals.

#A driver circuit includes a first differential input stage, a second differential input stage, a current mirror part, push-pull type output stage, first and second auxiliary current sources, a power output auxiliary circuit, and a controlling part.

#The first differential input stage has a first MOS transistor and a second MOS transistor. The first MOS transistor whose gate is controlled by an electric potential at an input terminal is connected across a first current source and a third node. The second MOS transistor whose gate is controlled by an electric potential at an output terminal is connected across the first current source and a fourth node. The second differential input stage has a third MOS transistor and a fourth MOS transistor. The third MOS transistor whose conductivity is controlled by the electric current at the input terminal is connected across a first node and a second current source. The fourth MOS transistor whose gate is controlled by the electric potential at the output terminal is connected to a second node and the second current source. The current mirror part supplies a first power supply current to the second node and the fourth node. The current mirror part also supplies a second power supply current whose magnitude corresponds to the first power supply current to the first and third node.