Back to results
US 8,044,833 B2Granted
High speed serializer
AssigneeRaytheon Company
InventorJeong-Gyun Shin
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a high speed serializer for multiplexing 2N data inputs, N being a positive integer, comprises one less than 2N multiplexing cells arranged in N stages. The stages are numbered 1 through N, and the output of the Nth stage is a serial transmission and the inputs of the 1st stage are the 2N data inputs. Each stage comprises half as many multiplexing cells as the preceding stage. Additionally, each multiplexing cell comprises a multiplexer that comprises a pair of inputs and an output. 2N-2 of the multiplexing cells in the first stage further comprise a latch, and the output of the latch is coupled to an input of the multiplexer.
Claims34
A high speed serializer for multiplexing 2N data inputs, N being a positive integer, the serializer comprising:
- one less than 2N multiplexing cells arranged in N stages, the stages numbered 1 through N, wherein the output of the Nth stage is a serial transmission and the inputs of the 1st stage are the 2N data inputs;
- wherein each stage comprises half as many multiplexing cells as the preceding stage;
- and
- wherein each multiplexing cell comprises a multiplexer, the multiplexer comprising a pair of inputs and an output, and at most 2N-2 of the multiplexing cells in the first stage further comprise a latch, wherein the output of the latch is coupled to an input of the multiplexer.
1 more element
A high speed serializer for multiplexing 2N data inputs, N being a positive integer, the serializer comprising:
- one less than 2N multiplexing cells arranged in N stages, the stages numbered 1 through N, wherein the output of the Nth stage is a serial transmission and the inputs of the 1st stage are the 2N data inputs;
- wherein each stage comprises half as many multiplexing cells as the preceding stage;
- wherein each multiplexing cell comprises a multiplexer, the multiplexer comprising a pair of inputs and an output, and 2N-2 of the multiplexing cells in the first stage further comprise a latch, wherein the output of the latch is coupled to an input of the multiplexer;
- wherein the multiplexer in the Nth stage is configured for receiving a clock signal and the multiplexers in each stage preceding the Nth stage are configured for receiving one of two clock signals;
- wherein half of the multiplexers in each stage preceding the Nth stage are configured for receiving the same one of two clock signals;
- wherein the clock signals received by the multiplexers in each stage preceding the Nth stage operate at half the frequency of the clock signals received by the multiplexers in the subsequent stage;
- and
- wherein each latch is configured to receive a clock signal having the opposite state of the clock signal received by the multiplexer to which it is coupled.
5 more elements
A method for multiplexing 2N data inputs, N being a positive integer, wherein the method comprises:
- generating a serial transmission using one less than 2N multiplexing cells arranged in N stages, the stages numbered 1 through N, wherein the output of the Nth stage is the serial transmission and the inputs of the 1st stage are the 2N data inputs;
- wherein each stage comprises half as many multiplexing cells as the preceding stage;
- and
- wherein each multiplexing cell comprises a multiplexer, the multiplexer comprising a pair of inputs and an output, and at most 2N-2 of the multiplexing cells in the first stage further comprise a latch, wherein further the output of the latch is coupled to an input of the multiplexer.
1 more element
A method for multiplexing 2N data inputs, N being a positive integer, wherein the method comprises:
- generating a serial transmission using one less than 2N multiplexing cells arranged in N stages, the stages numbered 1 through N, wherein the output of the Nth stage is the serial transmission and the inputs of the 1st stage are the 2N data inputs;
- wherein each stage comprises half as many multiplexing cells as the preceding stage;
- wherein each multiplexing cell comprises a multiplexer, the multiplexer comprising a pair of inputs and an output, and 2N-2 of the multiplexing cells in the first stage further comprise a latch, wherein further the output of the latch is coupled to an input of the multiplexer;
- wherein the multiplexer in the Nth stage is configured for receiving a clock signal and the multiplexers in each stage preceding the Nth stage are configured for receiving one of two clock signals;
- wherein half of the multiplexers in each stage preceding the Nth stage are configured for receiving the same one of two clock signals;
- wherein the clock signals received by the multiplexers in each stage preceding the Nth stage operate at half the frequency of the clock signals received by the multiplexers in the subsequent stage;
- and
- wherein each latch is configured to receive a clock signal having the opposite state of the clock signal received by the multiplexer to which it is coupled.
5 more elements
A high speed serializer for multiplexing 2N data inputs, N being a positive integer, the serializer comprising:
- a plurality of multiplexing cells arranged in N stages, the stages numbered 1 through N, wherein the output of the Nth stage is a serial transmission and the inputs of the 1st stage are the 2N data inputs;
- wherein each multiplexing cell comprises at least a multiplexer, the multiplexer comprising a pair of inputs and an output;
- wherein the multiplexer in the Nth stage is configured for receiving a clock signal and the multiplexers in each stage preceding the Nth stage are configured for receiving one of two clock signals;
- wherein half of the multiplexers in each stage preceding the Nth stage are configured for receiving the same one of two clock signals;
- wherein the clock signals received by the multiplexers in each stage preceding the Nth stage operate at half the frequency of the clock signals received by the multiplexers in the subsequent stage;
- and
- wherein the two clock signals received by the multiplexers in each stage preceding the Nth stage are skewed from each other by a half cycle of the clock signal of the subsequent stage.
4 more elements
A method for multiplexing 2N data inputs, N being a positive integer, wherein the method comprises:
- generating a serial transmission using a plurality of multiplexing cells arranged in N stages, the stages numbered 1 through N, wherein the output of the Nth stage is serial transmission and the inputs of the 1st stage are the 2N data inputs,
- wherein each multiplexing cell comprises at least a multiplexer, the multiplexer comprising a pair of inputs and an output,
- wherein the multiplexer in the Nth stage is configured for receiving a clock signal and the multiplexers in each stage preceding the Nth stage are configured for receiving one of two clock signals,
- wherein half of the multiplexers in each stage preceding the Nth stage are configured for receiving the same one of two clock signals,
- wherein the clock signals received by the multiplexers in each stage preceding the Nth stage operate at half the frequency of the clock signals received by the multiplexers in the subsequent stage, and
- wherein the two clock signals received by the multiplexers in each stage preceding the Nth stage are skewed from each other by a half cycle of the clock signal of the subsequent stage.
3 more elements
A high speed serializer for multiplexing 4 data inputs, the serializer comprising:
- a first multiplexer comprising a pair of inputs and an output;
- a latch comprising an input and an output, wherein the output of the latch is coupled to an input of the first multiplexer;
- a second multiplexer comprising a pair of inputs and an output;
- and
- a third multiplexer comprising a first input, a second input, and an output,
- wherein:
- the output of the first multiplexer is coupled directly to the first input of the third multiplexer;
- the output of the second multiplexer is coupled directly to the second input of the third multiplexer;
- and
- the output of the third multiplexer is a serial transmission.
7 more elements
A high speed serializer for multiplexing 4 data inputs, the serializer comprising:
- a first multiplexer comprising a pair of inputs and an output;
- a latch comprising an input and an output, wherein the output of the latch is coupled to an input of the first multiplexer;
- a second multiplexer comprising a pair of inputs and an output;
- and
- a third multiplexer comprising a first input, a second input, and an output,
- wherein:
- the output of the first multiplexer is coupled to the first input of the third multiplexer;
- the output of the second multiplexer is coupled to the second input of the third multiplexer;
- the output of the third multiplexer is a serial transmission;
- wherein the first multiplexer is configured for receiving a first clock signal, the second multiplexer is configured for receiving a second clock signal, the third multiplexer is configured for receiving a third clock signal, and the latch is configured for receiving a fourth clock signal,
- wherein:
- the first and second clock signals operate at half the frequency of the third clock signal;
- and
- the fourth clock signal has the opposite state of the first clock signal.
11 more elements
A method for multiplexing 4 data inputs, wherein the method comprises:
- generating a serial transmission using:
- a first multiplexer comprising a pair of inputs and an output;
- a latch comprising an input and an output, wherein the output of the latch is coupled to an input of the first multiplexer;
- a second multiplexer comprising a pair of inputs and an output;
- and
- a third multiplexer comprising a first input, a second input, and an output,
- wherein:
- the output of the first multiplexer is directly coupled to the first input of the third multiplexer;
- the output of the second multiplexer is directly coupled to the second input of the third multiplexer;
- and
- the output of the third multiplexer is the serial transmission.
8 more elements
A method for multiplexing 4 data inputs, wherein the method comprises:
- generating a serial transmission using:
- a first multiplexer comprising a pair of inputs and an output,
- a latch comprising an input and an output, wherein the output of the latch is coupled to an input of the first multiplexer;
- a second multiplexer comprising a pair of inputs and an output;
- and
- a third multiplexer comprising a first input, a second input, and an output,
- wherein:
- the output of the first multiplexer is coupled to the first input of the third multiplexer;
- the output of the second multiplexer is coupled to the second input of the third multiplexer;
- and
- the output of the third multiplexer is the serial transmission;
- wherein the first multiplexer is configured for receiving a first clock signal, the second multiplexer is configured for receiving a second clock signal, the third multiplexer is configured for receiving a third clock signal, and the latch is configured for receiving a fourth clock signal,
- wherein:
- the first and second clock signals operate at half the frequency of the third clock signal;
- and
- the fourth clock signal has the opposite state of the first clock signal.
13 more elements
Dependencies are inferred from the claim text.