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US 8,044,801 B1Granted
RFID tag with double-switch rectifier
AssigneeImpinj, Inc.
InventorsJohn D. Hyde, Ronald A. Oliver, Charles J. T. Peach
Life of this patent
Estimating the term…
Abstract
The present disclosure provides a power rectifier for a Radio Frequency Identification tag circuit. The power rectifier is constructed from a pair of complementary MOS transistors. Gates of the transistors have predetermined voltages applied to them. The applied voltages bias the transistors to near their active operating regions, while an additional RF control signal is being applied to only one of the gates of the transistors in the complementary pair.
Claims16
A power rectifier for a Radio Frequency Identification tag, comprising:
- a first antenna input node configured to receive wirelessly an alternating signal;
- and
- a plurality of serially coupled stages, each including components, at least one of the stages coupled to the antenna input node, and including a first Double-Switch element that includes:
- a first transistor having an input terminal, an output terminal and a first gate, and
- a second transistor having an input terminal, an output terminal, and a second gate,
- in which the input terminal of the second transistor is connected to the output terminal of the first transistor to form a first intermediate node that is not connected to any of the remaining components, and
- one of the first gate and the second gate is coupled to the first antenna input node, while the other one of the first gate and the second gate is not biased by an alternating signal.
4 more elements
A power rectifier for a Radio Frequency Identification tag, comprising:
- a first antenna input node configured to receive wirelessly a first alternating signal;
- a second antenna input node configured to receive wirelessly a second alternating signal;
- and
- a plurality of serially coupled dual stages, each including components, at least one of the dual stages coupled to both the first and second antenna input nodes, and including a first dual Double-Switch element that includes:
- a first transistor having an input terminal, an output terminal, and a first gate, and
- a second transistor having an input terminal, an output terminal, and a second gate,
- in which the input terminal of the second transistor is connected to the output terminal of the first transistor to form a first intermediate node that is not connected to any of the remaining components, and
- a third transistor having an input terminal, an output terminal and a third gate, and a fourth transistor having an input terminal, an output terminal, and a fourth gate,
- in which the input terminal of the fourth transistor is connected to the output terminal of the third transistor to form a second intermediate node that is not connected to any of the remaining components, and
- one of the first gate and the second gate is coupled to the first antenna input node, while the other one of the first gate and the second gate is not biased by an alternating signal, and
- one of the third gate and the forth gate is coupled to the second antenna input node, while the other one of the third gate and the forth gate is not biased by an alternating signal.
8 more elements
Dependencies are inferred from the claim text.