Method and apparatus for applying clock phase and frequency offset
AssigneeAgere Systems Inc.
InventorStanley Jeh-Chun Ma
Life of this patent
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Abstract
Various apparatuses and methods for offsetting the phase and/or frequency of a clock signal are disclosed herein. For example, some embodiments provide an apparatus for generating a clock signal, including a quadrature delay circuit connected to an input clock signal. The quadrature delay circuit outputs components of the input clock signal with different phase shifts. A first amplitude modulator is connected to the first output of the quadrature delay circuit, and a second amplitude modulator is connected to the second output of the quadrature delay circuit. A summer combines the output of the first and second amplitude modulators.
Claims25
An apparatus for generating a clock signal, the apparatus comprising:
- a quadrature delay circuit having an input, a first output and a second output, the input being connected to an input clock signal, wherein the quadrature delay circuit is adapted to provide a first component of the input clock signal on the first output and a second component of the input clock signal on the second output, wherein the first component and the second component each have a different phase shift;
- a first amplitude modulator having an input and an output, the input being connected to the first output of the quadrature delay circuit;
- a second amplitude modulator having an input and an output, the input being connected to the second output of the quadrature delay circuit;
- and
- a summer having a first input, a second input and a clock output, the first input being connected to the output of the first amplitude modulator, the second input being connected to the output of the second amplitude modulator;
- and
- a storage device having a clock source connected to a plurality of serializer/deserializers, wherein the quadrature delay circuit, first and second amplitude modulators and summer are connected between the clock source and at least one of the plurality of serializer/deserializers to provide a plurality of different frequency offsets in the plurality of serializer/deserializers.
A method of generating a clock, the method comprising:
- generating at least two phase offset components from a frequency offset input, said generating comprising:
- integrating the frequency offset input to generate a phase offset signal;
- and
- dividing the phase offset signal into a pair of phasors, wherein the pair of phasors have a same frequency and a different phase;
- and
- offsetting an input clock signal according to the frequency offset input, said offsetting comprising:
- dividing the input clock signal into an in-phase phasor and a quadrature phasor;
- controlling an amplitude of each of the in-phase phasor and the quadrature phasor based on the pair of phasors
- combining the amplitude-controlled in-phase and quadrature phasors to form an output clock signal;
- and
- providing a pulse at the frequency offset input, wherein the pulse causes a phase offset between the output clock signal and the input clock signal, while leaving the output clock signal at a frequency of the input clock signal.
A serial advanced technology attachments (SATA) storage drive, comprising:
- a clock source;
- a serializer/deserializer having a plurality of data channels;
- and
- a spread spectrum clock generator in each of the plurality of data channels, each of the spread spectrum clock generators being connected to the clock source, each of the spread spectrum clock generators comprising:
- a delay circuit having an input connected to the clock source, a first output and a second output, wherein the first and second outputs have a phase offset;
- a first variable gain amplifier connected to the first output;
- a second variable gain amplifier connected to the second output;
- a summer connected to the first and second variable gain amplifiers;
- a spectrum spreading input;
- an integrator connected to the spectrum spreading input;
- and
- a phase offset divider connected to the integrator, the phase offset divider having a first phase offset output and a second phase offset output, the first and second phase offset outputs having a common frequency and a different phase, the first phase offset output being connected to a gain control input on the first variable gain amplifier, the second phase offset output being connected to a gain control input on the second variable gain amplifier, wherein a data rate in each of the plurality of data channels in the SATA storage drive is independently and continuously modulated by the spread spectrum generators.
Dependencies are inferred from the claim text.