Back to results
US 8,044,729 B2Granted
Phase locked loop and voltage controlled oscillator thereof
AssigneePhison Electronics Corp.
InventorWei-Yung Chen
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneePhison Electronics Corp.
InventorWei-Yung Chen
Estimating the term…
A phase locked loop (PLL) and a voltage controlled oscillator (VCO) thereof are provided. The VCO includes a ring oscillator circuit and a control circuit. The ring oscillator circuit is used for providing an output clock signal; and the control circuit is coupled to the ring oscillator circuit, and used for receiving an output voltage to respectively provide a first voltage-frequency gain and a second voltage-frequency gain so as to control a frequency of the output clock signal provided by the ring oscillator circuit, wherein the first voltage-frequency gain is larger than the second voltage-frequency gain.
A voltage controlled oscillator (VCO), comprising:
A phase locked loop (PLL), comprising:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
From the US filing history. Foreign family members aren’t listed.
Astable circuits: ring oscillators
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: using special…
Concerning mainly the controlled oscillator of the loop: the oscillator comprising a ring oscillator
Indexing scheme relating to automatic control of frequency or phase and to synchronisation: phase locked loops with a controlled oscillator having…
About 3 years 4 months of term left · ends 17 Feb 2030 (estimated)
This application claims the priority benefit of Taiwan application serial no. 98134313, filed on Oct. 9, 2009. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
1. Field of the Invention
The present invention relates to a phase locked loop (PLL), more particularly, to a PLL with a low-variation and stable loop bandwidth.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 is a diagram of a conventional phase locked loop (PLL).
FIG. 2 is a block diagram of a PLL according to an exemplary embodiment of the present invention.
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
Embodiments of the present invention may comprise any one or more of the novel features described herein, including in the Detailed Description, and/or shown in the drawings. As used herein, “at least one”, “one or more”, and “and/or” are open-ended expressions that are both conjunctive and disjunctive in operation. For example, each of the expressions “at least on of A, B and C”, “at least one of A, B, or C”, “one or more of A, B, and C”, “one or more of A, B, or C” and “A, B, and/or C” means A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B and C together.
It is to be noted that the term “a” or “an” entity refers to one or more of that entity. As such, the terms “a” (or “an”), “one or more” and “at least one” can be used interchangeably herein. In addition, in the exemplary embodiments below, when a device is described as being “connected” or “coupled” to another device, the device can be directly connected or coupled to another device, or other devices can be arranged therebetween.