Phased locked loop circuit including voltage controlled ring oscillator

A phased locked loop circuit, comprising:

• a phase detector to compare a feedback clock signal with a reference clock signal and to output a difference signal;
• a charge pump to output a signal based on the difference signal;
• a filter to smooth the signal and to output a voltage control signal;
• and
• a voltage controlled ring oscillator to output a clock signal corresponding to the feedback clock signal based on the voltage control signal,
• wherein the voltage controlled ring oscillator includes:
• a plurality of Current Mode Logic type (CML-type) differential amplifiers which are ring-connected;
• and
• a plurality of variable capacitance elements being respectively connected to said plurality of amplifiers and having capacitances varied by the voltage control signal,
• a plurality of load resistors respectively connected to said plurality of amplifiers;
• a plurality of tail current sources respectively connected to said plurality of amplifiers;
• and
• a plurality of offset capacitance elements respectively connected in parallel with said plurality of variable capacitance elements, a capacitance of each of the plurality of offset capacitance elements being capable of being variable-controlled independent from said variable capacitance.