Oscillator signal generation with spur mitigation in a wireless communication device

An integrated circuit comprising:

• a phase-frequency detector for receiving a reference signal and a feedback signal and providing a detector signal indicative of phase difference between the reference signal and the feedback signal;
• a charge pump for generating an error signal based on the detector signal;
• a loop filter for filtering the error signal and providing a control signal for an oscillator;
• a divider for receiving an oscillator signal from the oscillator, dividing the oscillator signal in frequency, and providing the feedback signal, wherein at least one of the charge pump, the loop filter, and the divider has multiple settings for a parameter other than overall divider ratio, the multiple settings being selectable for each of multiple frequency channels and comprising a first set of settings resulting in lower spur levels at a first frequency channel than a second set of settings, the second set of settings resulting in lower spur levels at a second channel frequency than the first set of settings;
• and
• a memory storing a table of the PLL settings for the multiple frequency channels, the PLL settings comprising PLL loop bandwidth settings, frequency equation settings, frequency division scheme settings, low side or high side injection settings, overall divider ratio settings, and VCO biasing settings.

A method comprising:

• selecting a frequency channel from among multiple frequency channels, each frequency channel being associated with a set of phase-locked loop (PLL) settings for at least one parameter in addition to overall divider ratio, the multiple frequency channels being associated with at least two different sets of PLL settings;
• storing a set of PLL settings in a table in a memory to reduce spur levels for the selected frequency channel, the PLL settings comprising PLL loop bandwidth settings, frequency equation settings, frequency division scheme settings, low side or high side injection settings, overall divider ratio settings, and VCO biasing settings;
• and
• generating an oscillator signal for the selected frequency channel based on the set of PLL settings.

An apparatus for wireless communication, comprising:

• means for selecting a frequency channel from among multiple frequency channels, each frequency channel being associated with a set of phase-locked loop (PLL) settings for at least one parameter in addition to overall divider ratio and chosen to mitigate the effect of spurs, the multiple frequency channels being associated with at least two different sets of PLL settings;
• means for storing a set of PLL settings in a table in a memory to reduce spur levels for the selected frequency channel, the PLL settings comprising PLL loop bandwidth settings, frequency equation settings, frequency division scheme settings, low side or high side injection settings, overall divider ratio settings, and VCO biasing settings;
• and
• means for generating an oscillator signal for the selected frequency channel based on the set of PLL settings.

A non-transitory computer-readable medium having instructions stored thereon, which when executed by a processor, causes the following to occur:

• selecting a frequency channel from among multiple frequency channels, each frequency channel being associated with a set of phase-locked loop (PLL) settings for at least one parameter in addition to overall divider ratio, the multiple frequency channels being associated with at least two different sets of PLL settings;
• determining a set of PLL settings to reduce spur levels for the selected frequency channel;
• retrieving the set of PLL settings stored in a table in a memory, the set of PLL settings comprising PLL loop bandwidth settings, frequency equation settings, frequency division scheme settings, low side or high side injection settings, overall divider ratio settings, and VCO biasing settings;
• and
• generating an oscillator signal for the selected frequency channel based on the set of PLL settings.