US 8,044,712 B2Granted

Circuit and method for improved frequency resolution of wide-bandwidth digitally programmable RC active filters

AssigneeTexas Instruments Incorporated

InventorSalvatore Finocchiaro

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Abstract

An active RC filter (20) includes a first resistive element (23) and a first capacitor array (10/50) which co-acts with the first resistive element (23) to determine a bandwidth characteristic of the programmable active RC filter circuit (20). The total filter capacitance is programmed by switching various first capacitors (4-0, 1, 2 . . . 7) of a first capacitor array (10) in parallel between first and second terminals of the first capacitor array in response to a control word (B0, 1, 2 . . . 7) to determine a first portion of the bandwidth characteristic, and by switching various second capacitors (7-0, 1, 2 . . . 6) of the first capacitor array between the first and second terminals of the first capacitor array in parallel with various ones of the first capacitors (4-0, 1, 2 . . . 7) of the first capacitor array (10) in response to less significant bits (B0, 1, 2 . . . 6) of the control word (B0, 1, 2 . . . 7) to determine a second portion of the bandwidth characteristic.

Claims12

Dependent claims

An apparatus comprising:

a resistive element;
a capacitive array having a first terminal and an second terminal, wherein the resistive element is coupled to the first terminal of the capacitive array, and wherein the capacitive array includes:
a first set of binarily weighted capacitive elements, wherein each capacitive element from the first set of capacitive elements is coupled to the first terminal of the capacitive array;
a first set of switches, wherein each switch from the first set of switches is associated with at least one of the capacitive elements from the first set of capacitive elements, and wherein each switch is coupled between its capacitive element and the second terminal of the capacitive array, and wherein the first set of switches is controlled by a first binary control word having N bits;
a second set of binarily weighted capacitive elements, wherein each capacitive element from the second set of capacitive elements is coupled to the first terminal of the capacitive array;
and
a second set of switches, wherein each switch from the second set of switches is associated with at least one of the capacitive elements from the second set of capacitive elements, and wherein each switch is coupled between its capacitive element and the second terminal of the capacitive array, and wherein the second set of switches is controlled by a second control word having N−1 bits;
and
logic circuitry having a plurality of AND-gates that are arranged to receive the first binary control word and to generate the second binary control word from the first binary control word, wherein the plurality of AND-gates includes a set of N−1 AND-gates that are each associated with at least one of the switches from the second set of switches and that each receive the Nth bit from the first binary control word.

6 more elements

An apparatus comprising:

an amplifier having a first input terminal and a second input terminal;
a first resistive element is coupled to the first input terminal of the amplifier;
a second resistive element that that is coupled to the second input terminal of the amplifier;
a capacitive array having a first terminal and an second terminal, wherein the first terminal of the capacitive array is coupled to the first resistive element, and wherein the second terminal of the capacitive array is coupled to the second resistive element, and wherein the capacitive array includes:
a first set of binarily weighted capacitive elements, wherein each capacitive element from the first set of capacitive elements is coupled to the first terminal of the capacitive array;
a first set of switches, wherein each switch from the first set of switches is associated with at least one of the capacitive elements from the first set of capacitive elements, and wherein each switch is coupled between its capacitive element and the second terminal of the capacitive array, and wherein the first set of switches is controlled by a first binary control word having N bits;
a second set of binarily weighted capacitive elements, wherein each capacitive element from the second set of capacitive elements is coupled to the first terminal of the capacitive array;
and
a second set of switches, wherein each switch from the second set of switches is associated with at least one of the capacitive elements from the second set of capacitive elements, and wherein each switch is coupled between its capacitive element and the second terminal of the capacitive array, and wherein the second set of switches is controlled by a second control word having N−1 bits;
and
logic circuitry having a plurality of AND-gates that are arranged to receive the first binary control word and to generate the second binary control word from the first binary control word, wherein the plurality of AND-gates includes a set of N−1 AND-gates that are each associated with at least one of the switches from the second set of switches and that each receive the Nth bit from the first binary control word.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/287,853Filed 14 Oct 2008
Published: US 2010/0090757 A115 Apr 2010
Granted: 25 Oct 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H03H 11/1291
Using amplifiers with feedback: current or voltage controlled filters
H03H 7/0153
Frequency selective two-port networks: electrical filters; Controlling thereof
H03J 2200/10
Indexing scheme relating to tuning resonant circuits and selecting resonant circuits: tuning of a resonator by means of digitally controlled…
H03H
Impedance networks