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US 8,044,711 B1Granted
Clock signal noise shaping
AssigneePericom Semiconductor Corp.
InventorsMichael Yimin Zhang, Tat C. Choi
Life of this patent
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Abstract
A method and apparatus for clock signal noise shaping are described. Embodiments of a clock circuit include a filter coupled to receive an input clock signal and to provide an output clock signal. The filter filters noise of the input clock signal to shape the noise to provide the output clock signal. In a method for adjustment of phase noise, input clock signaling having the phase noise is obtained, and the input clock signal is filtered to adjust the phase noise to provide output clock signaling.
Claims15
A clock circuit, comprising:
- a filter coupled to receive a first input clock signal, wherein the first input clock signal is noncompliant with a phase parameter of a serial link specification for a serial link owing to phase noise;
- the filter coupled to provide an output clock signal, wherein the phase noise of the first input clock signal is shaped by the filter to reform the first input signal in order to provide the output clock signal for compliance with the phase parameter of the serial link specification for the serial link for at least a gigabit per second speed;
- the filter for filtering noise of the first input clock signal to shape the phase noise to provide the output clock signal;
- and
- a lock loop circuit directly connected to the filter to receive the output clock signal.
2 more elements
A method for adjustment of phase noise, comprising:
- obtaining input clock signaling having the phase noise;
- filtering the input clock signal to adjust the phase noise to provide output clock signaling;
- wherein the filtering includes:
- programming the filter to shape the phase noise to reform the input clock signaling;
- and
- shaping the phase noise responsive to the programming to at least meet a specification for the phase noise for a serial link for at least a gigabit per second speed;
- providing the output clock signal directly to a phase lock loop;
- programming a counter of the phase lock loop;
- translating a first frequency of the input clock signaling to a second frequency different from the first frequency;
- and
- outputting operative clock signaling at the second frequency.
8 more elements
Dependencies are inferred from the claim text.