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US 8,044,699 B1Granted
Differential high voltage level shifter
AssigneePolar Semiconductor, Inc.
InventorDavid W. Kelly
Life of this patent
Estimating the term…
Abstract
A level-shift circuit translates a control signal to a level-shifted output. The level-shift circuit includes a pulse generator circuit for providing Set and Reset pulses based on the control signal and a level-shift circuit for translating the Set and Reset pulses to level-shifted Set and Reset pulses. First and second differential detectors are connected to monitor the level-shifted Set and Reset pulses to provide detection of communicated Set and Reset pulses despite the presence of transients in the level-shift circuit. A gate drive circuit employs the Set and Reset pulses communicated by the differential detectors to generate a gate drive signal.
Claims18
A level-shift circuit for translating a control signal to a level-shifted output signal, the level-shift circuit comprising:
- a pulse generator circuit for receiving the control signal and generating in response to the control signal a Set pulse and a Reset pulse;
- a voltage translation circuit connected to receive the Set and Reset pulses from the pulse generator circuit and to generate in response a level-translated Set pulse and a level-translated Reset pulse, wherein the level-translated Set pulse and level-translated Reset pulse are derived from a bootstrap voltage node having a voltage greater than a voltage of the Set pulse and the Reset pulse, wherein the voltage translation circuit includes:
- a first resistor network connected between the bootstrap voltage node and a first node for providing the level-translated Set pulse;
- a second resistor network connected between the bootstrap voltage node and a second node for providing the level-translated Reset pulse;
- a first high-voltage transistor connected between the first resistor network and a reference node and controlled to be On or Off by the Set pulse provided by the pulse generator circuit, wherein when the first high-voltage transistor is On a current path between the bootstrap voltage node and the reference node through the first resistor network provides the level-translated Set pulse;
- a second high-voltage transistor connected between the second resistor network and a reference node and controlled to be On or Off by the Reset pulse provided by the pulse generator circuit, wherein when the second transistor is On a current path between the bootstrap voltage node and the reference node through the second resistor network provides the level-translated Reset pulse;
- a common-mode transient detection circuit connected to monitor voltages across the first and second resistor networks and to provide an output in response to detected common-mode transients;
- and
- a gain reduction circuit connected to reduce gain associated with translation of the Set and Reset pulses to level-translated Set and Reset pulses in response to a common-mode transient detected by the common-mode transient detection circuit;
- a first differential detector connected to receive the level-translated Set pulse and the level-translated Reset pulse, wherein the first differential detector generates a logic high output when a threshold voltage difference is present between the level-translated Set pulse and the level-translated Reset pulse;
- a second differential detector connected to receive the level-translated Reset pulse and the level-translated Set pulse, wherein the second differential detector generates a logic high output when a threshold voltage difference is present between the level-translated Reset pulse and the level-translated Set pulse;
- and
- a gate drive circuit for generating a gate drive signal based on the outputs provided by the first differential detector and the second differential detector.
10 more elements
A high-voltage driver circuit for supplying a drive output to a power switch connected to supply a high-voltage power input to an output terminal, the high-voltage driver circuit comprising:
- an input terminal for receiving a power supply voltage;
- a bootstrap diode connected between the input terminal and a bootstrap voltage;
- a capacitor connected between the bootstrap terminal and the output terminal to provide a bootstrap voltage having a magnitude related to a magnitude of the output terminal;
- a pulse generator circuit for receiving a low-voltage control signal and generating in response to the control signal a Set pulse and a Reset pulse;
- a voltage translation circuit connected to receive the Set and Reset pulses and to provide in response a level-translated Set pulse and a level-translated Reset pulse, wherein the level-translated Set pulse and level-translated Reset pulse are derived from the bootstrap voltage;
- a first differential detector connected to receive the level-translated Set pulse and the level-translated Reset pulse, and to provide in response a first output indicating whether a level-translated Set pulse has been detected based on a comparison of the level-translated Set pulse and the level-translated Reset pulse;
- a second differential detector connected to receive the level-translated Set pulse and the level-translated Reset pulse, and to provide in response a second output indicating whether a level-translated Reset pulse has been detected based on a comparison of the level-translated Set pulse and the level-translated Reset pulse;
- a memory circuit for receiving the first and second outputs from the first and second differential detectors, respectively, and for providing in response a level-shifted control signal;
- and
- a gate drive circuit connected to receive the level-shifted control signal from the memory circuit and for providing in response a drive output to the power switch.
7 more elements
A level-shift circuit for translating a control signal to a level-shifted output signal, the level-shift circuit comprising:
- a pulse generator circuit for receiving the control signal and generating in response to the control signal a Set pulse and a Reset pulse;
- a voltage translation circuit connected to receive the Set and Reset pulses from the pulse generator circuit and to generate in response a level-translated Set pulse and a level-translated Reset pulse, wherein the level-translated Set pulse and level-translated Reset pulse are derived from a bootstrap voltage node having a voltage greater than a voltage of the Set pulse and the Reset pulse;
- a common-mode transient detection circuit connected to monitor translation of the level-translated Set pulse and the level-translated Reset pulse and to provide an output in response to detected common-mode transients;
- a gain reduction circuit connected to reduce gain associated with translation of the Set and Reset pulses by the voltage translation circuit to level-translated Set and Reset pulses in response to a common-mode transient detected by the common-mode transient detection circuit;
- a first differential detector connected to receive the level-translated Set pulse and the level-translated Reset pulse, wherein the first differential detector generates a logic high output when a threshold voltage difference is present between the level-translated Set pulse and the level-translated Reset pulse;
- a second differential detector connected to receive the level-translated Reset pulse and the level-translated Set pulse, wherein the second differential detector generates a logic high output when a threshold voltage difference is present between the level-translated Reset pulse and the level-translated Set pulse;
- and
- a gate drive circuit for generating a gate drive signal based on the outputs provided by the first differential detector and the second differential detector.
5 more elements
Dependencies are inferred from the claim text.