Back to results
US 8,044,696 B2Granted
Delay circuit having long delay time and semiconductor device comprising the same
AssigneeSamsung Electronics Co., Ltd.
InventorsTae-Hyung Kim, Min-Su Kim
Life of this patent
Estimating the term…
Abstract
A delay circuit has a long delay time and a semiconductor device includes the delay circuit. The delay circuit includes an inverter circuit unit having at least one inverter. Each of the inverters includes a first transistor connected to a supply voltage and a second transistor connected to a ground voltage. The inverter circuit unit receives a first signal and outputs a second signal by delaying the first signal. At least one capacitor unit is connected to an input terminal of the inverter such that a loading capacitance of the inverter circuit unit is increased.
Claims10
A delay circuit delaying an input signal and generating an output signal, the delay circuit being aligned within a standard cell having a standardized size, comprising:
- a first active region electrically connected to a supply voltage, a first transistor of a first inverter is aligned in the first active region;
- a second active region electrically connected to a ground voltage, a second transistor of the first inverter is aligned in the second active region;
- a third active region in which a first capacitor is aligned, the first capacitor providing a first loading capacitance to an input node of the first inverter, and
- a first gate line crossing the first through third active regions and forming gate electrodes of the first and second transistors and a first electrode of the first capacitor.
1 more element
A delay circuit comprising:
- an inverter circuit unit comprising at least one inverter stage, each inverter stage comprising:
- a pull-up transistor that switches a first voltage, and
- a pull-down transistor that switches a second voltage, the pull-down transistor being coupled in series to the pull-up transistor;
- and
- a resistance unit connected to at least one inverter stage and having a predetermined resistance independent of an input signal to the inverter circuit unit,
- wherein the inverter circuit unit, in response to receiving the input signal, outputs an output signal having a delay from the input signal, the delay corresponding to the predetermined resistance,
- wherein the resistance unit includes at least one PMOS transistor connected between the first voltage and the pull-up transistor and at least one NMOS transistor connected between the second voltage and the pull-down transistor,
- wherein a gate electrode of the at least one NMOS transistor is directly connected to the first voltage and a gate electrode of the at least one PMOS transistor is connected to a node between the pull-down transistor and second voltage,
- wherein the first voltage is a supply voltage, and the second voltage is a ground voltage,
- wherein the at least one PMOS transistor comprises a first PMOS transistor connected between the first voltage and the pull-up transistor,
- wherein the at least one NMOS transistor comprises a first NMOS transistor and a second NMOS transistor connected in series between the second voltage and the pull-down transistor, and
- wherein:
- the gate of the first NMOS transistor is directly connected to the first voltage,
- the gate of the first NMOS transistor is connected to the gate of the second NMOS transistor, and
- a gate of the first PMOS transistor is connected to a node between the pull-down transistor and the second voltage.
12 more elements
A delay circuit comprising:
- an inverter circuit unit comprising at least one inverter stage, each inverter stage comprising:
- a pull-up transistor that switches a first voltage, and
- a pull-down transistor that switches a second voltage, the pull-down transistor being coupled in series to the pull-up transistor;
- and
- a resistance unit connected to at least one inverter stage and having a predetermined resistance independent of an input signal to the inverter circuit unit,
- wherein the inverter circuit unit, in response to receiving the input signal, outputs an output signal having a delay from the input signal, the delay corresponding to the predetermined resistance,
- wherein the resistance unit includes at least one PMOS transistor connected between the first voltage and the pull-up transistor and at least one NMOS transistor connected between the second voltage and the pull-down transistor,
- wherein a gate electrode of the at least one NMOS transistor is directly connected to the first voltage and a gate electrode of the at least one PMOS transistor is connected to a node between the pull-down transistor and second voltage,
- wherein the first voltage is a supply voltage, and the second voltage is a ground voltage,
- wherein the at least one PMOS transistor comprises a first PMOS transistor connected between the first voltage and the pull-up transistor,
- wherein the at least one NMOS transistor comprises a first NMOS transistor and a second NMOS transistor connected in series between the second voltage and the pull-down transistor, and
- wherein:
- a gate of the first NMOS transistor and a gate of the second NMOS transistor are connected to a node between the pull-up transistor and the first PMOS transistor, and
- a gate of the first PMOS transistor is connected to a node between the pull-down transistor and the second voltage.
11 more elements
Dependencies are inferred from the claim text.