Output voltage slew rate control in hard disk motor drive

A driver circuit configured to generate an output signal Vout having a controlled slew rate, the output signal Vout being generated at an output node of the driver circuit, the driver circuit comprising:

• a first transistor having (i) a first node coupled to a high supply voltage and (ii) a second node coupled to the output node of the driver circuit, the first transistor being configured to pass the high supply voltage to the output node based on a first gate voltage on a gate of the first transistor;
• a second transistor having (i) a first node coupled to a low supply voltage and (ii) a second node coupled to the output node of the driver circuit, the second transistor being configured to pass the low voltage to the output node based on a second gate voltage on a gate of the second transistor;
• and
• a logic block comprising
• a first fast pull-up logic circuitry configured to pull up the first gate voltage from the low supply voltage to a first intermediate voltage between the low supply voltage and the high supply voltage, and
• a first pull-up pre-driver control circuit configured to pull up the first gate voltage from the first intermediate voltage to the high supply voltage,
• wherein the logic block is configured to control the slew rate of the output signal Vout by (i) controlling a slew rate of the first gate voltage on the gate of the first transistor, and (ii) controlling a slew rate of the second gate voltage on the gate of the second transistor.