US 8,044,687 B2Granted

Wide input common mode voltage comparator

AssigneeSemiconductor Manufacturing International (Shanghai) Corporation

InventorsTa Lee Yu, Qian Yu Yu

Life of this patent

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Abstract

A design for a wide input common mode voltage comparator is provided which reduces the delay between outputs from component comparators. The wide input common mode voltage comparator includes a first comparator configured to receive a differential input. The first comparator is further configured to accommodate high common mode voltages. The wide input common mode voltage comparator further includes a second comparator configured to receive the differential input. The first comparator is further configured to accommodate low common mode voltages. Additionally, the threshold voltages of the active devices within the comparator are between −100 to 100 mV. Furthermore, the wide input common mode voltage comparator includes a summing circuit configured to receive the outputs of the first and second comparators to create a single-ended output.

A wide input common mode voltage comparator comprising:

a high common mode voltage comparator comprising:
a bias NMOS transistor having a first source terminal coupled to ground;
a pair of differential NMOS transistors coupled to a first drain terminal of the bias NMOS transistor;
and
a first load block coupled to the bias pair of differential NMOS transistor;
a summing circuit;
a low common mode voltage comparator comprising:
a first native NMOS transistor serving as a bias transistor and being coupled to ground at its source terminal;
second and third native NMOS transistors forming a differential pair, the second and third native NMOS transistors coupled to the drain terminal of the first native NMOS transistor and receiving an input differential voltage as gate voltages, the second and the third NMOS transistors having a threshold voltage between −100 to 100 mV;
and
a second load block comprising:
a first PMOS transistor coupled at its drain terminal to the drain terminal of the second native NMOS transistor;
the drain terminal of the first PMOS transistor additionally coupled to the gate terminal of the first PMOS transistor;
a second PMOS transistor coupled at its drain terminal to the drain terminal of the third native NMOS transistor;
the drain terminal of the second PMOS transistor additionally coupled to the gate terminal of the second PMOS transistor;
a third PMOS transistor coupled at its gate terminal to the gate terminal of the first PMOS transistor, the drain terminal of the third PMOS transistor coupled to a first output;
and
a fourth PMOS transistor coupled at its gate terminal to the gate terminal of the second PMOS transistor, the drain terminal of the fourth PMOS transistor coupled to a first output;
wherein:
the first, second, third, and fourth PMOS transistors are coupled to a voltage source at their source terminals;
the high common voltage comparator receives the input differential and generates a second output;
the summing circuit receives the first output and the second output and generates a third output based on the first output and the second output.

19 more elements

Facts

Application

11/548,696Filed 11 Oct 2006

Priority

CN 2006 1 002632130 Apr 2006

Published

US 2008/0018362 A124 Jan 2008

Granted

25 Oct 2011

Term ends

Not estimatedThe source records don’t support an estimate.

Classification4 codes

H03K 19/018528
Of complementary type, e.g. CMOS: with at least one differential stage
H03K 5/003
Manipulating of pulses not covered by one of the other main groups of this subclass: changing the DC level
H03K 5/2472
The characteristic being amplitude: using field effect transistors
H03K
Pulse technique

Abstract

Claims11