FPGA having low power, fast carry chain

A field programmable gate array (FPGA) having a plurality of configurable logic blocks (CLBs) each comprising:

• a lookup table (LUT) having first and second data input terminals connected to receive respective first and second data signals transmitted thereto as inputs usable by a lookup function implemented in the LUT, and an output terminal for outputting a LUT result signal that is generated by the LUT based on the implemented lookup function of the LUT;
• and carry logic unit configured to perform carry bit generating operations that produce carry bits corresponding to carry input signals received by the carry logic unit, the carry logic unit having first, second and third carry logic input terminals for receiving the carry input signals and a carry output terminal for outputting the produced carry bits;
• wherein the first and second carry logic input terminals of the carry logic unit are connected respectively to the first and second data input terminals of the lookup table, wherein the plurality of configurable logic blocks (CLBs) includes a first CLB and a second CLB;
• wherein the respective lookup tables of the CLBs each includes a respective third data input terminal connected to receive respective third data signal transmitted thereto as an input usable by the respective lookup function implemented in the corresponding LUT of the respective CLB;
• and wherein the carry output terminal of the carry logic unit of the first CLB is programmably connectable to the third input terminal of the lookup table of the second CLB.

A field programmable gate array (FPGA) circuit comprising:

• a plurality of programmable lookup tables (LUTs) each having a respective LUT output terminal and respective first, second and third LUT input terminals disposed for receiving corresponding first, second and third LUT input term signals of the respective LUT;
• a carry bits generating chain having a plurality of carry bit generating units, each carry bit generating unit being associated with one of the LUTs and each carry bit generating unit having a respective unit output terminal and respective first, second and third carry unit input terminals disposed for receiving corresponding first, second and third carry input term signals of the respective carry bit generating unit, where the third carry unit input terminal of each carry bit generating unit in a continuous portion of the chain is connected to the unit output terminal of the previous unit in the chain,
• wherein the first and second carry unit input terminals of each unit are coupled to receive same respective first and second input signals as corresponding first and second LUT input terminals of the associated LUT, and
• wherein each carry bit generating unit includes a power cut off circuit configured to selectively cut off power consumption of a carry bit generating logic portion of the unit in response to a received depowering control signal, which depowering control signal is indicative of the respective carry bit generating unit not being used for carry bit generation.