Semiconductor memory device and on-die termination circuit
AssigneeSamsung Electronics Co., Ltd.
InventorsDong-Ho Hyun, Jin-Sung Kim
Life of this patent
Estimating the term…
Abstract
An on-die termination (ODT) circuit including drive signal generators, each drive signal generator configured to generate a corresponding plurality of ODT drive signals; and ODT drive units, each ODT drive unit configured to terminate a corresponding terminal with a termination resistance in response to the ODT drive signals of a corresponding drive signal generator. The drive signal generators are configured to supply the ODT drive signals to the ODT drive units to output a plurality of ODT control signals through the terminals in a test mode.
Claims11
An on-die termination (ODT) circuit, comprising:
- a plurality of drive signal generators, each drive signal generator configured to generate corresponding ODT drive signals;
- and
- a plurality of ODT drive units, each ODT drive unit configured to terminate a corresponding terminal with a termination resistance in response to the ODT drive signals of a corresponding drive signal generator,
- wherein the drive signal generators are configured to supply the ODT drive signals to the ODT drive units to output a plurality of ODT control signals through the terminals in a test mode, and
- wherein each drive signal generator is configured to receive a normal ODT enable signal and a dynamic ODT enable signal, to output a plurality of normal resistance code signals as the ODT drive signals when the normal ODT enable signal is activated, and to output a plurality of dynamic resistance code signals as the ODT drive signals when the dynamic ODT enable signal is activated.
A semiconductor memory device comprising:
- a command decoder configured to output a normal ODT enable signal and a dynamic ODT enable signal;
- a control signal generator configured to output a plurality of ODT control signals in response to the normal ODT enable signal and the dynamic ODT enable signal, and activate an ODT check signal during an ODT test mode operation;
- a plurality of drive signal generators, each drive signal generator configured to generate a corresponding plurality of ODT drive signals in response to the ODT control signals, the normal ODT enable signal, the dynamic ODT enable signal, and the ODT check signal;
- and
- a plurality of ODT drive units, each ODT drive unit configured to terminate a corresponding terminal with a termination resistance in response to the ODT drive signals of a corresponding drive signal generator;
- wherein the drive signal generators are configured to supply the ODT drive signals to the ODT drive units to output the ODT control signals through the terminals in a test mode.
Dependencies are inferred from the claim text.