On-die termination control circuit of semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorKyung-Whan Kim
Life of this patent
Estimating the term…
Abstract
On-die termination control circuit of semiconductor memory device includes a counter configured to count an external clock to output a first code, and to count an internal clock to output a second code, a transfer controller configured to determine whether to transfer the first code and the second code in response to a first termination command and a normal termination controller configured to compare the first code and the second code with each other to determine enabling/disabling timings of a termination operation in response to a second termination command.
Claims16
An on-die termination (ODT) control circuit of a semiconductor device, comprising:
- a counter configured to count a delayed internal clock to output a first code, and to count an internal clock to output a second code;
- a transfer controller configured to determine whether to transfer the first code and the second code in response to a first termination command;
- and
- a normal termination controller configured to determine enabling/disabling timings of a termination operation in response to a value of the first code and a value of the second code at an activation timing of a second termination command.
An ODT control circuit of a semiconductor device, comprising:
- a counter configured to count a delayed internal clock to output a first code, and to count an internal clock to output a second code;
- a transfer controller configured to be responsive to a first write command to transfer the first code and the second code for a predetermined time after the first write command;
- and
- a dynamic termination controller configured to determine enabling/disabling timings of a dynamic termination operation in response to a value of the first code and a value of the second code at an activation timing of a second write command.
An ODT control circuit of a semiconductor device, comprising:
- a counter configured to count a delayed internal clock to output a first code, and to count an internal clock to output a second code;
- a transfer controller configured to determine whether to transfer the first code and the second code in response to a first termination command, and to be responsive to a first write command to transfer the first code and the second code for a predetermined time after the first write command is input;
- a normal termination controller configured to determine enabling/disabling timings of a termination operation in response to a value of the first code and a value of the second code transferred from the transfer controller at an activation timing of a second termination command;
- and
- a dynamic termination controller configured to determine enabling/disabling timings of a dynamic termination operation in response to a value of the first code and a value of the second code transferred from the transfer controller at an activation timing of a second write command.
Dependencies are inferred from the claim text.