Testing apparatus with high efficiency and high accuracy
AssigneePrinceton Technology Corporation
InventorsYung-Yu Wu, Huei-Huang Chen, Wei-Fen Chiang
Life of this patent
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Abstract
A testing apparatus includes a public test board, a single DUT (device under test) test board and a holder. The public test board includes a plurality of public test channel sets each having a plurality of public signal terminals for receiving test signals. On the single DUT test board, a plurality first signal terminals are arranged according to the pin layout of a DUT, a plurality second signal terminals are arranged according to the terminal layout of a public channel set, and a plurality traces are arranged for electrically connecting corresponding first and second signal terminals. The holder can connect the pins of the DUT to corresponding first signal terminals.
Claims14
A testing apparatus with high efficiency and high accuracy comprising:
- a public test board having a plurality of public test channel sets, each public test channel set having a plurality of public signal terminals for receiving test signals;
- a first test board for testing a first device under test (DUT) having a plurality of pins;
- a first holder coupled to the first test board, the first holder including a plurality of sockets for containing the pins of the first DUT and a plurality of pins connected to the first test board;
- a second test board for testing a second DUT having a plurality of pins;
- a second holder coupled to the second test board, the second holder including a plurality of sockets for containing the pins of the second DUT and a plurality of pins connected to the second test board;
- wherein a plurality of first signal terminals are arranged on the first test board through a pin layout of the first DUT for respectively transmitting test signals to corresponding pins of the first DUT;
- wherein a plurality of second signal terminals are arranged on the first test board through a terminal layout of a first public test channel set of the plurality of public test channel sets for respectively receiving test signals transmitted from the first public test channel set;
- wherein a plurality of third signal terminals are arranged on the second test board through a pin layout of the second DUT for respectively transmitting test signals to corresponding pins of the second DUT;
- wherein a plurality of fourth signal terminals are arranged on the second test board through a terminal layout of a second public test channel set of the plurality of public test channel sets for respectively receiving test signals transmitted from the second public test channel set;
- wherein a plurality of first traces are arranged for electrically connecting the first signal terminals with the corresponding second signal terminals respectively;
- and
- wherein a plurality of second traces are arranged for electrically connecting the third signal terminals with the corresponding fourth signal terminals respectively.
Dependencies are inferred from the claim text.