Junction member comprising junction pads arranged in matrix and multichip package using same

A multichip package, comprising:

• a plurality of connecting terminals arranged in a peripheral area of the package, the connecting terminals including first connecting terminals arranged in a first-side peripheral area of the package and second connecting terminals arranged in a second-side peripheral area of the package opposite to the first-side peripheral area;
• a die pad;
• a first semiconductor chip disposed on the die pad, the first semiconductor chip including a central surface, and a peripheral surface on which a plurality of first pads are formed, the first semiconductor chip being located within the peripheral area including the connecting terminals;
• a second semiconductor chip disposed on the central surface of the first semiconductor chip, the second semiconductor chip being disposed closer to the first connecting terminals than the second connecting terminals, the second semiconductor chip including a plurality of second pads arranged in a central part thereof such that a distance from each second pad to a vertical edge of the second semiconductor chip that faces the first connecting terminals is substantially the same as a distance from each second pad to an opposite vertical edge of the second semiconductor chip that faces the second connecting terminals;
• a junction member disposed on the central surface of the first semiconductor chip, the junction member being disposed closer to the second connecting terminals than the first connecting terminals;
• and
• a resin encapsulating body which seals the first semiconductor chip, the second semiconductor chip, and the junction member;
• wherein the second semiconductor chip and the junction member are arranged along a first direction that extends from the first-side peripheral area to the second-side peripheral area of the package,
• wherein the junction member includes junction pads and pad connection portions, the junction pads consist of a plurality of junction pads all arranged in at least one rectangular matrix,
• wherein the junction pads including m rows, each row extending along the first direction, each row including n junction pads that are electrically connected to one another along the first direction by the pad connecting portions, the junction pads in each row being arranged side-by-side, each pad connecting portion in each row being disposed between two adjacent junction pads, a size of each junction pad being larger than a size of each pad connecting portion, a junction pad that is most adjacent to the second-side peripheral area in the row being directly connected to one of the first pads,
• wherein each of the matrices in which all the junction pads are arranged is a large m×n matrix where m and n are both integers greater than two,
• wherein the junction member further includes sub pads, the sub pads consisting of a plurality of sub pads all arranged in a rectangular matrix, wherein the matrix in which all the sub pads are arranged is a k×l array, where k and l are both integers greater than one,
• wherein the sub pads including l columns, each column extending along a second direction that is generally perpendicular to the first direction, each column including k junction pads that are electrically connected to one another along the second direction,
• wherein the junction pads are disposed in a first layer and the sub pads are disposed in a second layer underlying the first layer in a third direction generally perpendicular to both of the first direction and the second direction, and the junction member further comprises a plurality of sub-connecting portions each of which connects between first and second sub pads in the second direction, and wherein the junction pads and the sub pads do not short circuit to one another,
• wherein the second pads include a first central pad and a second central pad, the first central pad being directly connected to one of the first connecting terminals, the second central pad being connected to a junction pad in a row of the junction pads, and
• wherein the connecting terminals are lead terminals extending outward from the package, and each lead terminal has a connecting portion for connecting to the first semiconductor chip or the second semiconductor chip, and
• wherein each connecting portion of the first and second terminals is disposed at a level higher than the die pad and lower than the second semiconductor chip and the junction member.