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AssigneeHynix Semiconductor Inc.
InventorChang Jun Park
Estimating the term…
A semiconductor package includes a semiconductor chip provided with a bonding pad disposed over a surface thereof; a through electrode passing from the surface to a second surface opposing the first surface and connected electrically with the bonding pad; and a redistribution disposed at the second surface and connected electrically with the through electrode. An embodiment of the present invention is capable of significantly reducing the thickness and volume of the semiconductor package. It is also capable of high speed operation since the path of the signal inputted and/or outputted from the semiconductor package is shortened. It is capable of stacking easily at least two semiconductor packages having a wafer level, and it is capable of significantly reducing parasitic capacitance.
A semiconductor package comprising:
A semiconductor package comprising;
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
No references of this kind are recorded.
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
Of interconnections within wafers or substrates: the interconnections being through-semiconductor vias
The interconnections being through-semiconductor vias: comprising etching via holes through pads or through electrodes
Interconnections or connectors in packages: die-attach connectors
About 1 year 4 months of term left · ends 24 Feb 2028 (estimated)
The present application claims priority to Korean patent application number 10-2007-0080308 filed on Aug. 9, 2007, which is incorporated herein by reference in its entirety.
The present invention relates to a semiconductor package and a method for fabricating the same.
Recently, a development in a semiconductor manufacturing technology has allowed the manufacture of a semiconductor package having a semiconductor device adapted to process more data within a short time.
FIG. 1 is a plan view illustrating a semiconductor package in accordance with an embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line I-I′ in FIG. 1.
FIG. 3 is a cross-sectional view taken along line II-II′ in FIG. 1.
FIG. 1 is a plan view illustrating a semiconductor package in accordance with an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line I-I′ in FIG. 1. FIG. 3 is a cross-sectional view taken along line II-II′ in FIG. 1. FIG. 4 is a rear view illustrating a rear surface of the semiconductor package shown in FIG. 1.
Referring to FIG. 1, the semiconductor package 100 includes a semiconductor chip 10, a through electrode 20, and a redistribution pattern 30. In addition, the semiconductor package 100 may further include a first insulation layer pattern 6, a second insulation layer pattern 8 and conductive balls 6a and 8b.
The semiconductor chip 10 has, for example, a rectangular shape. The semiconductor chip 10 having the rectangular shape has a first surface 1, a second surface 2 opposing to the first surface 1, and side surfaces 3.