Interposer, semiconductor chip mounted sub-board, and semiconductor package
AssigneeGenusion, Inc.
InventorsMoriyoshi Nakashima, Kazuo Kobayashi, Natsuo Ajika
Life of this patent
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Abstract
A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on. Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.
Claims20
A semiconductor package comprising:
- a package substrate;
- a first semiconductor bare chip mounted on a surface of the package substrate;
- an interposer arranged parallel to the package substrate, the interposer having an upper surface and a lower surface;
- a second semiconductor bare chip mounted on the lower surface of the interposer, the second semiconductor bare chip opposing to the first semiconductor bare chip;
- a plurality of first electrodes formed on the lower surface of the interposer, and electrically connected to the second semiconductor bare chip respectively;
- a plurality of second electrodes formed on the upper surface of the interposer and arranged in substantially matrix with a pitch greater than an electrode pitch of the second semiconductor bare chip;
- and
- a plurality of third electrodes formed on the upper surface of the interposer and arranged in line with a pitch smaller than the pitch of the plurality of second electrodes, and arranged along at least one side of the interposer;
- wherein,
- the package substrate and one of the plurality of third electrodes are electrically connected;
- and
- one of the plurality of the first electrodes, one of the plurality of second electrodes and one of the plurality of third electrodes are electrically connected together.
A semiconductor package comprising:
- a package substrate;
- a first semiconductor bare chip mounted on a surface of the package substrate, the first semiconductor bare chip having a bonding pad;
- a first wire electrically connecting the bonding pad of the first semiconductor bare chip and the package substrate;
- a spacer arranged over a part of the first semiconductor bare chip and not over the bonding pad of the first semiconductor bare chip;
- and
- a sealed sub-board mounted on the spacer, the sealed sub-board being larger than the spacer, the sealed sub-board comprising:
- a second semiconductor bare chip;
- a interposer having an upper surface and a lower surface on which the second semiconductor bare chip is mounted;
- a plurality of first electrodes formed on the lower surface, the plurality of first electrodes being electrically connected to the second semiconductor bare chip;
- a plurality of second electrodes formed on the upper surface and arranged in substantially matrix with a pitch greater than an electrode pitch of the second semiconductor bare chip;
- a plurality of third electrodes formed on the upper surface and arranged in line with a pitch smaller than the pitch of the plurality of second electrodes, the plurality of third electrodes arranged along at least one edge of the interposer;
- and
- a first resin for sealing the lower surface of the interposer and the second semiconductor bare chip,
- wherein:
- the sealed sub-board is stacked over the spacer;
- and
- one of the plurality of third electrodes and the package substrate are electrically connected by a second wire.
Dependencies are inferred from the claim text.