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US 8,044,487 B2Granted
Semiconductor device and method of manufacturing the same
AssigneeMitsubishi Electric Corporation
InventorsSatoshi Rittaku, Kazuhiro Shimizu
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AssigneeMitsubishi Electric Corporation
InventorsSatoshi Rittaku, Kazuhiro Shimizu
Estimating the term…
A semiconductor device including a high voltage element and a low voltage element, including: a semiconductor substrate having high voltage element region where the high voltage element is formed, and a low voltage element region where the low voltage element is formed; a first LOCOS isolation structure disposed in the high voltage element region; and a second LOCOS isolation structure disposed in the low voltage element region, wherein the first LOCOS isolation structure includes a LOCOS oxide film formed on a surface of the semiconductor substrate and a CVD oxide film formed on the LOCOS oxide film, and the second LOCOS isolation structure includes a LOCOS oxide film.
A semiconductor device that comprises a high voltage element and a low voltage element, said device comprising:
A semiconductor device having a high voltage element and a low voltage element, the semiconductor device comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
Of double-diffused metal oxide semiconductor [DMOS] FETs: of lateral dmos [ldmos] fets
The components including insulated gates, e.g. IGFETs: manufacturing their gate insulating layers
The components including insulated gates, e.g. IGFETs: manufacturing their interconnections or electrodes, e.g. source or drain electrodes
About 2 months of term left · ends 20 Dec 2026 (estimated)
The disclosure of Japanese Patent Application No. 2006-37391 filed on Feb. 15, 2006 including specification, drawings and claims is incorporated herein by reference in its entirely.
1. Field of the Invention
The present invention is related to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device, such as a high voltage IC equipped with a high voltage element and a low voltage element, and a method of manufacturing the same.
FIG. 1 is a cross sectional view of a semiconductor device according to an embodiment 1 of the present invention;
FIGS. 2A through 2G show cross sectional views of steps for manufacturing the semiconductor device according to the embodiment 1 of the present invention;
FIGS. 3A through 3D show cross sectional views of other steps for manufacturing the semiconductor device according to the embodiment 1 of the present invention;
FIG. 1 is a cross sectional view of the semiconductor device according to the embodiment 1 of the present invention, generally denoted at 100. The semiconductor device 100 includes a high voltage element region 110 in which there is a horizontal MOS transistor (high voltage element) and a low voltage element region 120 in which there is a CMOS transistor (low voltage element).
The semiconductor device 100 includes a p− silicon substrate 1. An n+ buried diffusion layer 2 and an n− epitaxial layer 3 are formed on the silicon substrate 1.
In the high voltage element region 110, a p− diffusion region 4 which will serve as a well region is formed in the epitaxial layer 3. An n+ diffusion region 5 and a p+ diffusion region 6 are formed in the diffusion region 4. The n+ diffusion region 5 and the p+ diffusion region 6 will serve as source regions. For inter-element isolation, the surface of the epitaxial layer 3 includes a silicon oxide film 9a which is formed by a LOCOS method. The silicon oxide film 9a has the same film thickness as that of a silicon oxide film 9b, which is described later, located in the low voltage element region 120.