Semiconductor device

#This application claims priority to Japanese Patent Application No. 2008-263592 filed on Oct. 10, 2008, the disclosure of which including the specification, the drawings, and the claims is hereby incorporated by reference in its entirety.

#The present disclosure relates to an electrode pad structure for semiconductor devices.

#In recent years, there is a demand for a reduction in height of a chip including a wiring layer of a CCD (charge coupled device) or an imaging sensor in view of a relationship between the height and an optical characteristic thereof, in addition to improvements in function and scale of integration of a semiconductor device. Therefore, it is necessary to reduce the thickness of the wiring layer as well in the future. Wirings may be made of Cu in a state-of-the-art process. In this case, a Cu film is formed by plating before removal by Chemical Mechanical Polishing (CMP).

#FIG. 1 is a plan view showing an overall configuration of a semiconductor device according to a first embodiment of the present disclosure.

#FIGS. 2A and 2B are a plan view and a cross-sectional view showing a pad structure for the semiconductor device of the first embodiment, respectively.

#FIGS. 3A to 3D are plan views each showing a portion of a semiconductor device according to a variation of the first embodiment of the present disclosure.

#Hereinafter, a semiconductor device according to a first embodiment of the present disclosure will be described with reference to the accompanying drawings.

#FIG. 1 is a plan view showing an overall configuration of the semiconductor device of the first embodiment. The semiconductor device 50 of FIG. 1 has a cell region 51 for a CCD, an imaging sensor or the like which is provided at a center portion of the device, and pad arrangement regions 52 provided at a peripheral portion of the device. Note that, in the semiconductor device 50 of FIG. 1, the pad arrangement regions 52 are provided along four sides of the device. Alternatively, when the number of pads is small, the pad arrangement regions 52 may be provided along two sides of the device. Alternatively, when the number of pads is large, pads may be arranged in two stages in each pad arrangement region 52. In this case, the pads may be arranged in a staggered manner.

#In the semiconductor device 50 of this embodiment, a height of the device needs to be reduced so as to ensure a satisfactory optical characteristic of a CCD, an imaging sensor or the like provided in the cell region 51. Therefore, it is necessary to reduce a thickness of the wiring layer as well, which may lead to a malfunction. To prevent this, a pad structure according to the present disclosure described below is applied.