Semiconductor device and method of fabricating the same
AssigneeHynix Semiconductor Inc.
InventorByung-Duk Lee
Life of this patent
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Abstract
A semiconductor device with reduced contact resistance between a substrate and a plug includes a gate electrode disposed over the substrate, the plug formed over the substrate at both sides of the gate electrode and having a sidewall with a positive slope, a capping layer disposed between the gate electrode and the plug, and a gate hard mask layer whose sidewall disposed over the gate electrode is extended to a top surface of the capping layer. By employing the capping layer having a sidewall with a negative slope, the plug having the sidewall with a positive slope can be formed regardless of a shape or profile of the sidewall of the gate electrode. As a result, the contact area between the substrate and the plug is increased.
Claims15
A method of fabricating a semiconductor device, the method comprising:
- forming a conductive layer over a substrate;
- forming a photoresist pattern over the conductive layer;
- selectively etching the conductive layer using the photoresist pattern as an etch barrier to form a trench having a sidewall with a negative slope, thereby forming a plug having a sidewall with a positive slope and a gate electrode simultaneously;
- forming a capping layer by filling the trench between the plug and the gate electrode;
- and
- forming a gate hard mask layer over the gate electrode, wherein a sidewall of the gate hard mask layer extends to a top surface of the capping layer.
A method of fabricating a semiconductor device, the method comprising:
- forming a first conductive layer over a substrate;
- selectively etching the first conductive layer to simultaneously form a first gate electrode and a plug whose sidewall has a positive slope;
- forming a capping layer between the plug and the first gate electrode;
- recessing the plug and the first gate electrode by a certain thickness using the capping layer as an etch barrier, thereby forming a resultant structure;
- sequentially forming a barrier metal layer and a second conductive layer over a whole surface of the resultant structure;
- performing a planarization process until the capping layer is exposed, thereby forming a second gate electrode;
- and
- forming a gate hard mask layer over the second gate electrode that is formed over the first gate electrode, wherein a sidewall of the gate hard mask layer extends to a top surface of the capping layer.
Dependencies are inferred from the claim text.