Non-volatile memory device
AssigneeHynix Semiconductor Inc.
InventorJae Chul Om
Life of this patent
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Abstract
A non-volatile memory device having a SONOS structure and a manufacturing method thereof, where a conductive layer is formed between a charge trap layer and a blocking insulation layer of the SONOS structure. Therefore, when a voltage is applied to a gate, the conductive layer undergoes voltage distributions. Accordingly, a desired voltage can be applied to the blocking insulation layer, the charge trap layer and the tunnel insulating layer by controlling the effective oxide thickness (EOT) of the blocking insulation layer and the EOT of the charge trap layer and the tunnel insulating layer. It is therefore possible to improve the erase speed of a cell.
Claims9
A non-volatile memory device comprising:
- a tunnel insulating layer formed over a semiconductor substrate;
- a charge trap layer formed on the tunnel insulating layer;
- a blocking gate formed over the charge trap layer;
- a blocking insulation layer formed over the blocking gate;
- a capping polysilicon layer formed over the blocking insulating layer;
- and
- a gate electrode formed over the capping layer,
- wherein the blocking gate is for reducing a voltage applied to the blocking insulation layer during an erase operation, and
- wherein the charge trap layer is formed of silicon nitride for storing charges.
Dependencies are inferred from the claim text.