Semiconductor wafer with electrically connected contact and test areas

An electronic device comprising:

• a semiconductor chip having a top side that defines a plane, the semiconductor chip having an arrangement of contact areas and test areas which are arranged in a common plane that is parallel to the plane of the top side of the semiconductor chip and are in each case electrically conductively connected to one another via a conduction web that lies in the common plane, the contact areas being arranged in a passive, first region extending from a top side to a bottom side of the semiconductor chip, the passive first region having no active components of an integrated circuit, wherein the test areas are sealed and the contact areas are not sealed;
• a plurality of bonding balls arranged on the contact areas;
• the test areas being arranged in an active, second region of the top side of the semiconductor chip, the active second region having active components of an integrated circuit;
• the test areas and contact areas being formed in the same interconnect plane;
• the test areas having a length (lp) being at least approximately 1.5 times greater than a width (bp) thereof, and the contact areas being square with a width approximately equal to the width (bp) of the test areas;
• an insulating layer situated between the top side and a lower plane;
• through contacts extending through a portion of the insulating layer directly below the conduction web and extending from the conduction web to the lower plane, the through contacts being connected to interconnects that are connected to electrodes of the components of the integrated circuit;
• wherein portions of the insulating layer directly below the contact areas and the test areas are free from the through contacts.

A semiconductor wafer comprising:

• a plurality of semiconductor chips each having a top side that defines a plane and a passive first region and an active second region, the semiconductor chips having an arrangement of contact areas and test areas which are arranged in a common plane that is parallel to the plane of the top side of the semiconductor chip and are electrically conductively connected to one another via a conduction web that lies in the common plane, wherein the test areas are sealed and the contact areas are not sealed;
• a plurality of bonding balls arranged on the contact areas;
• the contact areas being arranged in the passive first region extending from the top side to a bottom side of the semiconductor chip, the passive first region having no active components of an integrated circuit, wherein the top sides of the contact areas are square and have width and height dimensions;
• and
• the test areas being arranged in the active second region of the top side of the semiconductor chip, the active second region having active components of an integrated circuit, wherein the top sides of the test areas are rectangular with larger length dimensions than the width dimensions of the contact areas;
• an insulating layer having through contacts arranged in the region of the conduction web and extending from the conduction web to a lower plane, the through contacts being connected to interconnects that are connected to electrodes of the components of the integrated circuit;
• wherein the contact areas and the test areas are free from the through contacts;
• each of the semiconductor chips being defined by a boundary extending around the respective semiconductor chip, the contact areas and the test areas are completely situated within the boundary the respective semiconductor chip.

A semiconductor chip comprising:

• a passive first region extending from a top side to a bottom side of the semiconductor chip, the top side of the semiconductor chip defining a plane;
• an active second region on the top side of the semiconductor chip;
• an arrangement of contact areas and test areas which are arranged in a common plane that is parallel to the plane of the top side of the semiconductor chip and are in each case electrically conductively connected to one another via a conduction web that lies in the common plane, the contact areas being arranged in the passive first region, the passive first region having no active components of an integrated circuit, the test areas being arranged in the active second region, the active second region having active components of an integrated circuit, wherein the test areas are sealed and the contact areas are not sealed, and wherein the top sides of the contact areas are square and have width and height dimensions and the top sides of the test areas are rectangular with larger length dimensions than the width dimensions of the contact areas;
• a plurality of bonding balls arranged on the contact areas;
• and
• an insulating layer situated between the top side and a lower plane;
• through contacts extending through a portion of the insulating layer directly below the conduction web and extending from the conduction web to the lower plane, the through contacts being connected to interconnects that are connected to electrodes of the components of the integrated circuit;
• wherein portions of the insulating layer directly below the contact areas and the test areas are free from the through contacts.