Process for through silicon via filling
AssigneeNovellus Systems, Inc.
InventorsJonathan D. Reid, Katie Qun Wang, Mark J. Wiley
Life of this patent
Estimating the term…
Abstract
A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.
Claims33
A method of plating a through silicon via for connecting at least two integrated circuits, wherein the through silicon via has a diameter of at least about 3 micrometers and a depth of at least about 20 micrometers, the method comprising:
- contacting a structure having a through silicon via hole with a plating solution having copper ions at a concentration of at least about 40 grams per liter and chloride ions at a concentration of no greater than about 2 ppm;
- and
- while contacting the structure, plating copper into the through silicon via hole to completely fill the through silicon via hole in a substantially void free manner,
- wherein a deposition rate during the plating is higher at the bottom of the through silicon via hole than near the opening of the through silicon via hole,
- wherein there is substantially no net deposition of copper onto field regions of the structure between a plurality of through silicon via holes while plating copper.
A method of plating a through silicon via for connecting at least two integrated circuits, wherein the through silicon via has a diameter of at least about 3 micrometers and a depth of at least about 20 micrometers, the method comprising:
- pretreating a seed layer deposited onto a structure;
- contacting the structure having a through silicon via hole with a plating solution having a copper ions at a concentration of between about 60 gram per liter and 100 gram per liter and chloride ions at a concentration of no greater than about 2 ppm;
- and
- while contacting the structure, plating copper into the through silicon via hole to completely fill the through silicon via hole in a substantially void free manner,
- wherein there is substantially no net deposition of copper onto field regions of the structure between a plurality of through silicon via holes while plating copper, and wherein a deposition rate during the plating is higher at the bottom of the through silicon via hole than near the opening of the through silicon via hole.
A copper plating solution for depositing copper in a through silicon via for connecting at least two integrated circuits, wherein the through silicon via has a diameter of at least about 3 micrometers and a depth of at least about 20 micrometers, the copper plating solution comprising:
- copper ions at a concentration of at least about 40 grams per liter;
- sulfuric acid;
- an oxidizing agent for oxidizing the deposited copper on a wafer field at a rate of between about 200 Å/minute and 3000 Å/minute when a current is not applied to wafer, the oxidizing agent comprises one or more types of ions selected from the group consisting of:
- cerium ions and iron ions;
- and
- chloride ions at a concentration of no greater than about 2 ppm.
A method of plating a through silicon via for connecting at least two integrated circuits, wherein the through silicon via has a diameter of at least about 3 micrometers and a depth of at least about 20 micrometers, the method comprising:
- contacting a structure having a through silicon via hole with a plating solution having copper ions at a concentration of at least about 40 grams per liter, chloride ions at a concentration of no greater than about 2 ppm, and an oxidizing agent for oxidizing deposited copper on a wafer field at a rate of between about 200 Å/minute and 3000 Å/minute when a current is not applied to wafer, the oxidizing agent comprises one or more types of ions selected from the group consisting of:
- cerium ions and iron ions;
- and
- while contacting the structure, plating copper into the through silicon via hole to completely fill the through silicon via hole in a substantially void free manner,
- wherein a deposition rate during the plating is higher at the bottom of the through silicon via hole than near the opening of the through silicon via hole.
A method of plating a through silicon via for connecting at least two integrated circuits, wherein the through silicon via has a diameter of at least about 3 micrometers and a depth of at least about 20 micrometers, the method comprising:
- contacting a structure having a through silicon via hole with a plating solution having:
- copper ions at a concentration of at least about 40 grams per liter,
- chloride ions at a concentration of no greater than about 2 ppm,
- an oxidizing agent for oxidizing deposited copper on a wafer field at a rate of between about 200 Å/minute and 3000 Å/minute when a current is not applied to wafer, and
- a reducing agent having a concentration gradient in the through silicon via hole, wherein the reducing agent impacts oxidation of the copper;
- and
- while contacting the structure, plating copper into the through silicon via hole to completely fill the through silicon via hole in a substantially void free manner,
- wherein a deposition rate during the plating is higher at the bottom of the through silicon via hole than near the opening of the through silicon via hole.
Dependencies are inferred from the claim text.