US 8,043,918 B2Granted

Semiconductor device and its manufacturing method

AssigneeRenesas Electronics Corporation

InventorsTakashi Kuroi, Katsuyuki Horita, Masashi Kitazawa, Masato Ishibashi

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Abstract

To manufacture in high productivity a semiconductor device capable of securely achieving element isolation by a trench-type element isolation and capable of effectively preventing potentials of adjacent elements from affecting other nodes, a method of manufacturing the semiconductor device includes: a step of forming a first layer on a substrate; a step of forming a trench by etching the first layer and the substrate; a step of thermally oxidizing an inner wall of the trench; a step of depositing a first conductive film having a film thickness equal to or larger than one half of the trench width of the trench on the substrate including the trench; a step of removing a first conductive film from the first layer by a CMP method and keeping the first conductive film left in only the trench; a step of anisotropically etching the first conductive film within the trench to adjust the height of the conductive film to become lower than the height of the surface of the substrate; a step of depositing an insulating film on the first conductive film by the CVD method to embed the upper part of the first conductive film within the trench; a step of flattening the insulating film by the CMP method; and a step of removing the first layer.

Claims19

Dependent claims

A method of manufacturing a semiconductor device that includes an element isolation trench, the method comprising:

forming a first layer on a substrate;
etching the first layer and the substrate to form a trench in the substrate;
thermally oxidizing an inner wall of the trench;
depositing a first conductive film having a thickness equal to or larger than one half of width of the trench on the substrate including inside the trench;
removing the first conductive film on the first layer by chemical mechanical polishing such that the first conductive film remains in only the trench;
adjusting height of the first conductive film in the trench to be lower than a surface of the substrate by anisotropically etching the first conductive film;
depositing an insulating film on the substrate by chemical vapor deposition to cover an upper surface of the first conductive film in the trench;
flattening the insulating film by chemical mechanical polishing;
and
removing the first layer;
oxidizing the substrate to form an oxide-semiconductor insulating film;
forming a second conductive film on the oxide-semiconductor insulating film;
patterning the second conductive film and the oxide-semiconductor insulating film;
forming a first impurity diffusion layer with a first concentration that is self-aligned with the second conductive film in a region from the surface of the substrate to a first depth;
forming sidewalls on sides of the second conductive film;
and
forming a second impurity diffusion layer with a second concentration higher than the first concentration that is self-aligned with the second conductive film and the sidewalls in a region to a second depth deeper than the first depth from the surface of the substrate, a lower edge of the second impurity diffusion layer being lower than an upper edge of the first conductive film at a side of the trench.

14 more elements

A method of manufacturing a semiconductor device that includes an element isolation trench, the method comprising:

forming a first layer on a substrate;
etching the first layer and the substrate to form a trench in the substrate;
thermally oxidizing an inner wall of the trench;
depositing a semiconductor film on the substrate to fill the trench;
removing the semiconductor film on the first layer by chemical mechanical polishing such that the semiconductor film remains in only the trench;
adjusting height of the semiconductor film in the trench to be lower than a surface of the substrate by anisotropically etching the semiconductor film;
depositing an insulating film on the substrate by chemical vapor deposition to cover an upper surface of the semiconductor film in the trench;
flattening the insulating film by chemical mechanical polishing;
removing the first layer;
forming an impurity diffusion layer in a region from the surface of the substrate to a depth deeper than a bottom of the trench;
and
doping an impurity into the semiconductor film to form a first conductive film.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/840,430Filed 21 Jul 2010 · division
Priority: JP 2004-31015125 Oct 2004
Published: US 2010/0285651 A111 Nov 2010
Granted: 25 Oct 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 84/0149
The components including insulated gates, e.g. IGFETs: manufacturing their interconnections or electrodes, e.g. source or drain electrodes
H10D 84/0151
The components including insulated gates, e.g. IGFETs: manufacturing their isolation regions
H10D 84/0186
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their interconnections or electrodes, e.g. source or drain electrodes

Family

PCT/JP2005/019141Parent of this division · filed 18 Oct 2005
US 2010/0285651 A1Pre-grant publication · published 11 Nov 2010
Application11/577,878Parent of this division
US 7,791,163 B2Parent of this division
US 2007/0241373 A1Published application
US 8,043,918 B2This patent

From the US filing history. Foreign family members aren’t listed.