System and method for error correction and detection in a memory system

A memory controller comprising:

• an interface to a plurality of memory modules, the modules in communication with a plurality of memory devices;
• a plurality of error codes, associated with at least two distinct and functionally unique error checking means, each error code associated with a syndrome and a subset of the memory devices, and at least two of the subsets having memory devices in common with each other;
• and
• an amalgamating mechanism configured for utilizing at least two non-zero syndromes generated by the distinct and functionally unique error checking means to further extend overall error correction capabilities by enabling additional identification of possible failing memory devices located within intersecting subsets of the memory devices associated with the non-zero syndromes, and for allowing the memory system to continue to run unimpaired in the presence of failing memory devices;
• wherein the plurality of error codes include a RAID-3 error correction code applied to the memory devices organized in a row across multiple memory modules thus spanning a plurality of memory devices across memory modules and a RAID-6 error correction code applied to the memory devices organized in columns across a single memory module thus spanning only one memory module, where only a single data element is shared between any row and column.

A method for detecting and correcting errors in a memory system, the method comprising:

• detecting one or more errors in the memory system, the memory system including a plurality of memory modules having memory devices, the memory modules accessed in unison in response to memory commands, the memory system including a plurality of error codes associated with at least two distinct and functionally unique error checking means, each error code associated with a syndrome and a subset of the memory devices, and at least two of the subsets having memory devices in common with each other, the detecting comprising detecting that at least two of the syndromes are non-zero;
• identifying the type of errors by intersecting the subsets of the memory devices associated with each of the error codes having a non-zero syndrome to isolate the one or more errors to one or both of a memory device and a memory module;
• and
• correcting the one or more errors using the plurality of error codes while the memory system continues to run unimpaired in the presence of the errors;
• wherein the plurality of error codes include a RAID-3 error correction code applied to the memory devices organized in a row across multiple memory modules thus spanning a plurality of memory devices across memory modules and a RAID-6 error correction code applied to the memory devices organized in columns across a single memory module thus spanning only one memory module, where only a single data element is shared between any row and column.